Entity: reconfig_icap_wrapper

Diagram

positive MIN_DEPTH_OUT positive MIN_DEPTH_IN std_logic clk std_logic reset std_logic clk_icap std_logic write_put std_logic_vector(31 downto 0) write_data std_logic write_done std_logic read_got std_logic icap_busy std_logic icap_readback std_logic icap_partial_res std_logic write_full std_logic read_valid std_logic_vector(31 downto 0) read_data

Description

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Authors: Paul Genssler

Entity: Simple ICAP wrapper with a fifo interface and a few status signals

Description:

This module was designed to connect the Xilinx "Internal Configuration Access Port" (ICAP) to a PCIe endpoint on a Dini board. Tested on:

tbd

License:

Copyright 2007-2016 Technische Universitaet Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and

limitations under the License.

Generics

Generic name Type Value Description
MIN_DEPTH_OUT positive 256
MIN_DEPTH_IN positive 256

Ports

Port name Direction Type Description
clk in std_logic
reset in std_logic
clk_icap in std_logic clock signal for ICAP, max 100 MHz (double check with manual)
icap_busy out std_logic the ICAP is processing the data
icap_readback out std_logic high during a readback
icap_partial_res out std_logic high during reconfiguration
write_put in std_logic data in
write_full out std_logic
write_data in std_logic_vector(31 downto 0)
write_done in std_logic high pulse/edge after all data was written
read_got in std_logic data out
read_valid out std_logic
read_data out std_logic_vector(31 downto 0)

Signals

Name Type Description
reset_icap std_logic
write_done_d std_logic
write_done_edge std_logic
write_done_icapclk std_logic
in_data_valid std_logic
in_data_fill_state std_logic_vector(STATE_BITS -1 downto 0)
in_data_rden std_logic
in_data_start std_logic high after enough data was written into the pci->icap fifo
icap_rden std_logic icap wants some yummy data
in_data std_logic_vector(31 downto 0)
out_data_full std_logic
out_data_put std_logic
out_data std_logic_vector(31 downto 0)
icap_data_config std_logic_vector(31 downto 0)
icap_data_readback std_logic_vector(31 downto 0)
icap_csb std_logic
icap_rw std_logic
icap_data_config_r std_logic_vector(31 downto 0)
icap_data_readback_r std_logic_vector(31 downto 0)
icap_csb_r std_logic
icap_rw_r std_logic
fsm_status std_logic_vector(31 downto 0)
fsm_status_clk std_logic_vector(31 downto 0)
fsm_ready std_logic
fsm_ready_d std_logic

Constants

Name Type Value Description
STATE_BITS positive 2
state_almost_full std_logic_vector(STATE_BITS -1 downto 0) (0 => '0',
others => '1')

Processes

Description
buffer some data before starting the icap, icap needs to be sync'ed before it can be paused

Description
icap

Instantiations

Description
sync the written pci data into the user clk
writer: pci
reader: core

Description
sync data from this core to the pci bus
writer: core
reader: pci