Entity: stat_Histogram

Diagram

positive DATA_BITS positive COUNTER_BITS std_logic Clock std_logic Reset std_logic Enable std_logic_vector(DATA_BITS - 1 downto 0) DataIn T_SLM(2**DATA_BITS - 1 downto 0, COUNTER_BITS - 1 downto 0) Histogram

Description

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Authors: Patrick Lehmann

Entity: Creates a histogram of all input data

Description:

.. TODO:: No documentation available.

License:

Copyright 2007-2016 Technische Universitaet Dresden - Germany Chair of VLSI-Design, Diagnostics and Architecture

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and

limitations under the License.

Generics

Generic name Type Value Description
DATA_BITS positive 16
COUNTER_BITS positive 16

Ports

Port name Direction Type Description
Clock in std_logic
Reset in std_logic
Enable in std_logic
DataIn in std_logic_vector(DATA_BITS - 1 downto 0)
Histogram out T_SLM(2**DATA_BITS - 1 downto 0, COUNTER_BITS - 1 downto 0)

Signals

Name Type Description
HistogramMemory T_HISTOGRAM_MEMORY(2**DATA_BITS - 1 downto 0)

Types

Name Type Description
T_HISTOGRAM_MEMORY array(natural range <>) of unsigned(COUNTER_BITS downto 0)

Functions

Description
create matrix from vector-vector

Processes