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Authors: Patrick Lehmann

Entity: sync_Pulse_Altera

Description:

This is a multi-bit clock-domain-crossing circuit optimized for Altera FPGAs. It synchronizes multiple pulsed bits into the clock-domain Clock. The clock-domain boundary crossing is done by two synchronizer D-FFs. All bits are independent from each other. It generates 3 flip flops per input bit and notifies Quartus, that these flip flops are synchronizer flip flops. If you need a platform independent version of this synchronizer, please use PoC.misc.sync.Pulse, which internally instantiates this module if an Altera FPGA is detected.

.. ATTENTION:: Use this synchronizer for very short signals (pulse).

CONSTRAINTS:

License:

Copyright 2007-2016 Technische Universitaet Dresden - Germany Chair of VLSI-Design, Diagnostics and Architecture

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and

limitations under the License.