Entity: xil_Reconfigurator

Diagram

boolean DEBUG FREQ CLOCK_FREQ T_XIL_DRP_CONFIG_ROM CONFIG_ROM std_logic Clock std_logic Reset std_logic Reconfig std_logic_vector(log2ceilnz(CONFIG_ROM'length) - 1 downto 0) ConfigSelect T_XIL_DRP_DATA DRP_DataIn std_logic DRP_Ack std_logic ReconfigDone std_logic DRP_en T_XIL_DRP_ADDRESS DRP_Address std_logic DRP_we T_XIL_DRP_DATA DRP_DataOut

Description

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Authors: Patrick Lehmann

Entity: Reconfiguration engine for DRP enabled Xilinx primtives

Description:

Many complex primitives in a Xilinx device offer a Dynamic Reconfiguration Port (DRP) to reconfigure a primitive at runtime without reconfiguring the whole FPGA.

This module is a DRP master that can be pre-configured at compile time with different configuration sets. The configuration sets are mapped into a ROM. The user can select a stored configuration with ConfigSelect. Sending a strobe to Reconfig will start the reconfiguration process. The operation completes with another strobe on ReconfigDone.

License:

Copyright 2007-2016 Technische Universitaet Dresden - Germany Chair of VLSI-Design, Diagnostics and Architecture

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and

limitations under the License.

Generics

Generic name Type Value Description
DEBUG boolean FALSE
CLOCK_FREQ FREQ 100 MHz
CONFIG_ROM T_XIL_DRP_CONFIG_ROM (0 downto 0 => C_XIL_DRP_CONFIG_SET_EMPTY)

Ports

Port name Direction Type Description
Clock in std_logic
Reset in std_logic
Reconfig in std_logic
ReconfigDone out std_logic
ConfigSelect in std_logic_vector(log2ceilnz(CONFIG_ROM'length) - 1 downto 0)
DRP_en out std_logic
DRP_Address out T_XIL_DRP_ADDRESS
DRP_we out std_logic
DRP_DataIn in T_XIL_DRP_DATA
DRP_DataOut out T_XIL_DRP_DATA
DRP_Ack in std_logic

Signals

Name Type Description
State T_STATE DualConfiguration - Statemachine
NextState T_STATE
DataBuffer_en std_logic
DataBuffer_d T_XIL_DRP_DATA
ROM_Entry T_XIL_DRP_CONFIG
ROM_LastConfigWord std_logic
ConfigSelect_d std_logic_vector(ConfigSelect'range)
ConfigIndex_rst std_logic
ConfigIndex_en std_logic
ConfigIndex_us unsigned(CONFIGINDEX_BITS - 1 downto 0)

Constants

Name Type Value Description
CONFIGINDEX_BITS positive log2ceilnz(CONFIG_ROM'length)

Types

Name Type Description
T_STATE ( ST_IDLE,
ST_READ_BEGIN,
ST_READ_WAIT,
ST_WRITE_BEGIN,
ST_WRITE_WAIT,
ST_DONE )

Processes

Description
configuration index counter

Description
data buffer for DRP configuration words

Description
DRP read-modify-write statemachine