Entity: serv_synth_wrapper

Diagram

PRE_REGISTER RESET_STRATEGY WITH_CSR RF_WIDTH RF_L2D wire clk wire i_rst wire i_timer_irq wire rvfi_valid wire [31:0] i_ibus_rdt wire i_ibus_ack wire [31:0] i_dbus_rdt wire i_dbus_ack wire [RF_WIDTH-1:0] i_rdata wire [63:0] rvfi_order wire [31:0] rvfi_insn wire rvfi_trap wire rvfi_halt wire rvfi_intr wire [1:0] rvfi_mode wire [1:0] rvfi_ixl wire [4:0] rvfi_rs1_addr wire [4:0] rvfi_rs2_addr wire [31:0] rvfi_rs1_rdata wire [31:0] rvfi_rs2_rdata wire [4:0] rvfi_rd_addr wire [31:0] rvfi_rd_wdata wire [31:0] rvfi_pc_rdata wire [31:0] rvfi_pc_wdata wire [31:0] rvfi_mem_addr wire [3:0] rvfi_mem_rmask wire [3:0] rvfi_mem_wmask wire [31:0] rvfi_mem_rdata wire [31:0] rvfi_mem_wdata wire [31:0] o_ibus_adr wire o_ibus_cyc wire [31:0] o_dbus_adr wire [31:0] o_dbus_dat wire [3:0] o_dbus_sel wire o_dbus_we wire o_dbus_cyc wire [RF_L2D-1:0] o_waddr wire [RF_WIDTH-1:0] o_wdata wire o_wen wire [RF_L2D-1:0] o_raddr

Generics

Generic name Type Value Description
PRE_REGISTER 1 Register signals before or after the decoder 0 : Register after the decoder. Faster but uses more resources 1 : (default) Register before the decoder. Slower but uses less resources */
RESET_STRATEGY "MINI" Amount of reset applied to design "NONE" : No reset at all. Relies on a POR to set correct initialization values and that core isn't reset during runtime "MINI" : Standard setting. Resets the minimal amount of FFs needed to restart execution from the instruction at RESET_PC */
WITH_CSR 1
RF_WIDTH 2
RF_L2D $clog2((32+(WITH_CSR4))32/RF_WIDTH)

Ports

Port name Direction Type Description
clk input wire
i_rst input wire
i_timer_irq input wire
rvfi_valid input wire
rvfi_order output wire [63:0]
rvfi_insn output wire [31:0]
rvfi_trap output wire
rvfi_halt output wire
rvfi_intr output wire
rvfi_mode output wire [1:0]
rvfi_ixl output wire [1:0]
rvfi_rs1_addr output wire [4:0]
rvfi_rs2_addr output wire [4:0]
rvfi_rs1_rdata output wire [31:0]
rvfi_rs2_rdata output wire [31:0]
rvfi_rd_addr output wire [4:0]
rvfi_rd_wdata output wire [31:0]
rvfi_pc_rdata output wire [31:0]
rvfi_pc_wdata output wire [31:0]
rvfi_mem_addr output wire [31:0]
rvfi_mem_rmask output wire [3:0]
rvfi_mem_wmask output wire [3:0]
rvfi_mem_rdata output wire [31:0]
rvfi_mem_wdata output wire [31:0]
o_ibus_adr output wire [31:0]
o_ibus_cyc output wire
i_ibus_rdt input wire [31:0]
i_ibus_ack input wire
o_dbus_adr output wire [31:0]
o_dbus_dat output wire [31:0]
o_dbus_sel output wire [3:0]
o_dbus_we output wire
o_dbus_cyc output wire
i_dbus_rdt input wire [31:0]
i_dbus_ack input wire
o_waddr output wire [RF_L2D-1:0]
o_wdata output wire [RF_WIDTH-1:0]
o_wen output wire
o_raddr output wire [RF_L2D-1:0]
i_rdata input wire [RF_WIDTH-1:0]

Signals

Name Type Description
rf_wreq wire
rf_rreq wire
wreg0 wire [4+WITH_CSR:0]
wreg1 wire [4+WITH_CSR:0]
wen0 wire
wen1 wire
wdata0 wire
wdata1 wire
rreg0 wire [4+WITH_CSR:0]
rreg1 wire [4+WITH_CSR:0]
rf_ready wire
rdata0 wire
rdata1 wire

Constants

Name Type Value Description
CSR_REGS WITH_CSR*4

Instantiations