Entity: Ad9681
- File: Ad9681.vhd
Diagram
Description
Title :
File : Ad9681.vhd Author : Benjamin Reese bareese@slac.stanford.edu Company : SLAC National Accelerator Laboratory Created : 2014-01-14 Last update: 2021-04-09 Platform :
Standard : VHDL'93/02
Description:
Copyright (c) 2014 SLAC National Accelerator Laboratory
Generics
| Generic name | Type | Value | Description |
|---|---|---|---|
| TPD_G | time | 1 ns |
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| clkP | in | sl | |
| clkN | in | sl | |
| vin | in | RealArray(7 downto 0) | |
| dP | out | slv8array(1 downto 0) | |
| dN | out | slv8array(1 downto 0) | |
| dcoP | out | slv(1 downto 0) | |
| dcoN | out | slv(1 downto 0) | |
| fcoP | out | slv(1 downto 0) | |
| fcoN | out | slv(1 downto 0) | |
| sclk | in | sl | |
| sdio | inout | sl | |
| csb | in | sl |
Signals
| Name | Type | Description |
|---|---|---|
| wrEn | sl | ConfigSlave signals |
| addr | slv(12 downto 0) | |
| wrData | slv(31 downto 0) | |
| byteValid | slv(3 downto 0) | |
| r | ConfigRegType | |
| rin | ConfigRegType | |
| pllRst | sl | ----------------------------------------------------------------------------------------------- Output constants and signals ----------------------------------------------------------------------------------------------- constant DCLK_PERIOD_C : time := CLK_PERIOD_G / 7.0; |
| clk | sl | |
| locked | sl | |
| rst | sl | |
| clkFbOut | sl | |
| clkFbIn | sl | |
| dClkInt | sl | |
| dClk | sl | |
| fClkInt | sl | |
| fClk | sl | |
| dcoInt | sl | |
| dco | sl | |
| fcoInt | sl | |
| fco | sl | |
| serData | slv8array(1 downto 0) |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| PN_SHORT_TAPS_C | NaturalArray | (0 => 4, 1 => 8) |
X9+X5+1 |
| PN_SHORT_INIT_C | slv(8 downto 0) | "011011111" | |
| PN_LONG_TAPS_C | NaturalArray | (0 => 16, 1 => 22) |
X23+X18+1 |
| PN_LONG_INIT_C | slv(22 downto 0) | "01001101110000000101000" | |
| GLOBAL_CONFIG_INIT_C | GlobalConfigType | ( mode => "000", stabilizer => '1', clockDivRatio => "000", outputLvds => '0', outputInvert => '0', termination => "00", driveStrength => '0', lsbFirst => '0', outputMode => "011", pllLowRateMode => '0', sel2xFrame => '0', bits => "00", binFormat => '1', digitalFsAdj => "100") |
|
| CHANNEL_CONFIG_INIT_C | ChannelConfigType | ( chopMode => '0', pn23 => PN_LONG_INIT_C, resetPnLongGen => '0', pn9 => PN_SHORT_INIT_C, resetPnShortGen => '0', userTestMode => "00", outputTestMode => "0000", outputPhase => "0011", inputPhase => "000", userPattern1 => X"0000", userPattern2 => X"0000", offsetAdjust => X"00", outputReset => '0', powerDown => '0') |
|
| CONFIG_REG_INIT_C | ConfigRegType | ( sample => (others => "0000000000000000"), rdData => X"00000000", lsbFirst => '0', softReset => '0', channelConfigEn => "1111111111", tmpGlobal => GLOBAL_CONFIG_INIT_C, tmpChannel => CHANNEL_CONFIG_INIT_C, global => GLOBAL_CONFIG_INIT_C, channel => (others => CHANNEL_CONFIG_INIT_C), word => '0') |
Types
| Name | Type | Description |
|---|---|---|
| GlobalConfigType | ||
| ChannelConfigType | ||
| ChannelConfigArray | array (natural range <>) of ChannelConfigType | |
| ConfigRegType |
Processes
- unnamed: ( )
- comb: ( addr, r, vin, wrData, wrEn )
Description
----------------------------------------------------------------------------------------------- Configuration register logic -----------------------------------------------------------------------------------------------
- seq: ( fClk )
Instantiations
- CLK_BUFG: IBUFGDS
- plle2_adv_inst: PLLE2_ADV
- FB_BUFG: BUFG
- FCLK_BUFG: BUFG
- DCLK_BUFG: BUFG
- DCO_BUFG: BUFG
- FCO_BUFG: BUFG
- RstSync_1: surf.RstSync
- AdiConfigSlave_1: surf.AdiConfigSlave