Entity: AxiLiteAsyncTb
- File: AxiLiteAsyncTb.vhd
Diagram
Description
Company : SLAC National Accelerator Laboratory
Description: Testbench for design "AxiLiteAsync"
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Signals
| Name | Type | Description |
|---|---|---|
| sAxiClk | sl | [in] |
| sAxiClkRst | sl | [in] |
| sAxiReadMaster | AxiLiteReadMasterType | [in] |
| sAxiReadSlave | AxiLiteReadSlaveType | [out] |
| sAxiWriteMaster | AxiLiteWriteMasterType | [in] |
| sAxiWriteSlave | AxiLiteWriteSlaveType | [out] |
| mAxiClk | sl | [in] |
| mAxiClkRst | sl | [in] |
| mAxiReadMaster | AxiLiteReadMasterType | [out] |
| mAxiReadSlave | AxiLiteReadSlaveType | [in] |
| mAxiWriteMaster | AxiLiteWriteMasterType | [out] |
| mAxiWriteSlave | AxiLiteWriteSlaveType | [in] |
| intAxiReadMaster | AxiLiteReadMasterType | [out] |
| intAxiReadSlave | AxiLiteReadSlaveType | [in] |
| intAxiWriteMaster | AxiLiteWriteMasterType | [out] |
| intAxiWriteSlave | AxiLiteWriteSlaveType |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| TPD_G | time | 1 ns | |
| NUM_ADDR_BITS_G | natural | 32 | |
| PIPE_STAGES_G | integer range 0 to 16 | 0 |
Processes
- test: ( )
Instantiations
- U_AxiLiteCrossbar_1: surf.AxiLiteCrossbar
- U_AxiLiteAsync: surf.AxiLiteAsync
Description
[in]
component instantiation
- U_AxiDualPortRam_1: surf.AxiDualPortRam
Description
[in]
- U_ClkRst_1: surf.ClkRst
Description
[out]
- U_ClkRst_2: surf.ClkRst