Entity: AxiLiteIpBusBridgeTb

Diagram

Description

Company : SLAC National Accelerator Laboratory

Description: Simulation Testbed for testing the AxiLiteIpBusBridgeTb module

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Signals

Name Type Description
axilClk sl
axilRst sl
axilWriteMaster AxiLiteWriteMasterType
axilWriteSlave AxiLiteWriteSlaveType
axilReadMaster AxiLiteReadMasterType
axilReadSlave AxiLiteReadSlaveType
ipbRdata slv(31 downto 0)
ipbAck sl
ipbErr sl
ipbAddr slv(31 downto 0)
ipbWdata slv(31 downto 0)
ipbStrobe sl
ipbWrite sl
regWriteMaster AxiLiteWriteMasterType
regWriteSlave AxiLiteWriteSlaveType
regReadMaster AxiLiteReadMasterType
regReadSlave AxiLiteReadSlaveType

Constants

Name Type Value Description
GET_BUILD_INFO_C BuildInfoRetType toBuildInfo(BUILD_INFO_C)
MOD_BUILD_INFO_C BuildInfoRetType ( buildString => GET_BUILD_INFO_C.buildString,
fwVersion => GET_BUILD_INFO_C.fwVersion,
gitHash => x"1111_2222_3333_4444_5555_6666_7777_8888_9999_AAAA")
SIM_BUILD_INFO_C slv(2239 downto 0) toSlv(MOD_BUILD_INFO_C) create a fake githash
CLK_PERIOD_G time 10 ns
TPD_G time CLK_PERIOD_G/4

Processes

Description
------------------------------------------ Simulation AXI-Lite Register Transactions ------------------------------------------

Instantiations

Description

Axi-Lite to IP bus Bridge

Description

IP Bus to Axi-Lite Bridge

Description

Example Register Module