Package: AxiLitePkg
- File: AxiLitePkg.vhd
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| AXI_RESP_OK_C | slv(1 downto 0) | "00" | Access ok |
| AXI_RESP_EXOKAY_C | slv(1 downto 0) | "01" | Exclusive access ok |
| AXI_RESP_SLVERR_C | slv(1 downto 0) | "10" | Slave Error |
| AXI_RESP_DECERR_C | slv(1 downto 0) | "11" | Decode Error |
| AXI_LITE_READ_MASTER_INIT_C | AxiLiteReadMasterType | ( araddr => (others => '0'), arprot => (others => '0'), arvalid => '0', rready => '1' ) |
Initialization constants |
| AXI_LITE_READ_SLAVE_INIT_C | AxiLiteReadSlaveType | ( arready => '0', rdata => (others => '0'), rresp => (others => '0'), rvalid => '0' ) |
Initialization constants |
| AXI_LITE_READ_SLAVE_EMPTY_OK_C | AxiLiteReadSlaveType | axiLiteReadSlaveEmptyInit(rresp => AXI_RESP_OK_C) | |
| AXI_LITE_READ_SLAVE_EMPTY_SLVERR_C | AxiLiteReadSlaveType | axiLiteReadSlaveEmptyInit(rresp => AXI_RESP_SLVERR_C) | |
| AXI_LITE_READ_SLAVE_EMPTY_DECERR_C | AxiLiteReadSlaveType | axiLiteReadSlaveEmptyInit(rresp => AXI_RESP_DECERR_C) | |
| AXI_LITE_WRITE_MASTER_INIT_C | AxiLiteWriteMasterType | ( awaddr => (others => '0'), awprot => (others => '0'), awvalid => '0', wdata => (others => '0'), wstrb => (others => '1'), wvalid => '0', bready => '1' ) |
Initialization constants |
| AXI_LITE_WRITE_SLAVE_INIT_C | AxiLiteWriteSlaveType | ( awready => '0', wready => '0', bresp => (others => '0'), bvalid => '0' ) |
Initialization constants |
| AXI_LITE_WRITE_SLAVE_EMPTY_OK_C | AxiLiteWriteSlaveType | axiLiteWriteSlaveEmptyInit(bresp => AXI_RESP_OK_C) | |
| AXI_LITE_WRITE_SLAVE_EMPTY_SLVERR_C | AxiLiteWriteSlaveType | axiLiteWriteSlaveEmptyInit(bresp => AXI_RESP_SLVERR_C) | |
| AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C | AxiLiteWriteSlaveType | axiLiteWriteSlaveEmptyInit(bresp => AXI_RESP_DECERR_C) | |
| AXI_LITE_STATUS_INIT_C | AxiLiteStatusType | ( writeEnable => '0', readEnable => '0') |
|
| AXI_LITE_ENDPOINT_INIT_C | AxiLiteEndpointType | ( axiReadMaster => AXI_LITE_READ_MASTER_INIT_C, axiReadSlave => AXI_LITE_READ_SLAVE_INIT_C, axiWriteMaster => AXI_LITE_WRITE_MASTER_INIT_C, axiWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, axiStatus => AXI_LITE_STATUS_INIT_C) |
|
| AXI_LITE_REQ_INIT_C | AxiLiteReqType | ( request => '0', rnw => '1', address => (others => '0'), wrData => (others => '0')) |
|
| AXI_LITE_ACK_INIT_C | AxiLiteAckType | ( done => '0', resp => (others => '0'), rdData => (others => '0')) |
|
| AXIL_XBAR_CFG_DEFAULT_C | AxiLiteCrossbarMasterConfigArray(0 to 3) | ( 0 => (baseAddr => X"00000000", addrBits => 16, connectivity => X"FFFF"), 1 => (baseAddr => X"00010000", addrBits => 16, connectivity => X"FFFF"), 2 => (baseAddr => X"00020000", addrBits => 16, connectivity => X"FFFF"), 3 => (baseAddr => X"00030000", addrBits => 16, connectivity => X"FFFF")) |
Types
| Name | Type | Description |
|---|---|---|
| AxiLiteReadMasterType | Note: Any transaction that does not decode to a legal master interface destination, or programmers view register, receives a DECERR response. For an AHB master, the AXI DECERR is mapped back to an AHB ERROR. ------------------------------------------------------ AXI bus, read master signal record ------------------------------------------------------ Base Record | |
| AxiLiteReadMasterArray | array (natural range<>) of AxiLiteReadMasterType | Array |
| AxiLiteReadSlaveType | ------------------------------------------------------ AXI bus, read slave signal record ------------------------------------------------------ Base Record | |
| AxiLiteReadSlaveArray | array (natural range<>) of AxiLiteReadSlaveType | Array |
| AxiLiteWriteMasterType | ------------------------------------------------------ AXI bus, write master signal record ------------------------------------------------------ Base Record | |
| AxiLiteWriteMasterArray | array (natural range<>) of AxiLiteWriteMasterType | Array |
| AxiLiteWriteSlaveType | ------------------------------------------------------ AXI bus, write slave signal record ------------------------------------------------------ Base Record | |
| AxiLiteWriteSlaveArray | array (natural range<>) of AxiLiteWriteSlaveType | Array |
| AxiLiteStatusType | ||
| AxiLiteEndpointType | ------------------------------------------------------ AXI bus, read/write endpoint record, RTH 1/27/2016 ------------------------------------------------------ | |
| AxiLiteReqType | -------------------------------------------------------------------------------- Constants for endpoint abstractions (migrated from legacy AxiLiteMasterPkg.vhd) -------------------------------------------------------------------------------- | |
| AxiLiteAckType | ||
| AxiLiteCrossbarMasterConfigType | ----------------------------------------------------------------------------------------------- Crossbar Config Generic Types ----------------------------------------------------------------------------------------------- | |
| AxiLiteCrossbarMasterConfigArray | array (natural range <>) of AxiLiteCrossbarMasterConfigType |
Functions
- axiLiteReadSlaveEmptyInit ( rresp : slv(1 downto 0) := AXI_RESP_OK_C;
rdata : slv(31 downto 0) := (others => '0')) return AxiLiteReadSlaveType
- axiLiteWriteSlaveEmptyInit ( bresp : slv(1 downto 0) := AXI_RESP_OK_C) return AxiLiteWriteSlaveType
- axiWriteMasterInit (constant config : AxiLiteCrossbarMasterConfigArray) return AxiLiteWriteMasterArray
Description
Initilize masters with uppder address bits already set to configuration base address
- axiWriteMasterInit (constant config : AxiLiteCrossbarMasterConfigType) return AxiLiteWriteMasterType
- axiReadMasterInit (constant config : AxiLiteCrossbarMasterConfigArray) return AxiLiteReadMasterArray
- axiReadMasterInit (constant config : AxiLiteCrossbarMasterConfigType) return AxiLiteReadMasterType
- axiSlaveWaitWriteTxn ( signal axiWriteMaster : in AxiLiteWriteMasterType;
variable axiWriteSlave : inout AxiLiteWriteSlaveType;
variable writeEnable : inout sl) return ()
Description
Slave AXI Processing procedures
- axiSlaveWaitReadTxn ( signal axiReadMaster : in AxiLiteReadMasterType;
variable axiReadSlave : inout AxiLiteReadSlaveType;
variable readEnable : inout sl) return ()
- axiSlaveWaitTxn ( signal axiWriteMaster : in AxiLiteWriteMasterType;
signal axiReadMaster : in AxiLiteReadMasterType;
variable axiWriteSlave : inout AxiLiteWriteSlaveType;
variable axiReadSlave : inout AxiLiteReadSlaveType;
variable axiStatus : inout AxiLiteStatusType) return ()
- axiSlaveWriteResponse ( variable axiWriteSlave : inout AxiLiteWriteSlaveType;
axiResp : in slv(1 downto 0) := AXI_RESP_OK_C) return ()
- axiSlaveReadResponse ( variable axiReadSlave : inout AxiLiteReadSlaveType;
axiResp : in slv(1 downto 0) := AXI_RESP_OK_C) return ()
- axiSlaveRegister ( signal axiWriteMaster : in AxiLiteWriteMasterType;
signal axiReadMaster : in AxiLiteReadMasterType;
variable axiWriteSlave : inout AxiLiteWriteSlaveType;
variable axiReadSlave : inout AxiLiteReadSlaveType;
variable axiStatus : in AxiLiteStatusType;
addr : in slv;
offset : in integer;
reg : inout slv;
constAssign : in boolean := false;
constVal : in slv := "0") return ()
Description
Address decode procedures
- axiSlaveRegister ( signal axiReadMaster : in AxiLiteReadMasterType;
variable axiReadSlave : inout AxiLiteReadSlaveType;
variable axiStatus : in AxiLiteStatusType;
addr : in slv;
offset : in integer;
reg : in slv) return ()
- axiSlaveRegister ( signal axiWriteMaster : in AxiLiteWriteMasterType;
signal axiReadMaster : in AxiLiteReadMasterType;
variable axiWriteSlave : inout AxiLiteWriteSlaveType;
variable axiReadSlave : inout AxiLiteReadSlaveType;
variable axiStatus : in AxiLiteStatusType;
addr : in slv;
offset : in integer;
reg : inout sl;
constAssign : in boolean := false;
constVal : in sl := '0') return ()
- axiSlaveRegister ( signal axiReadMaster : in AxiLiteReadMasterType;
variable axiReadSlave : inout AxiLiteReadSlaveType;
variable axiStatus : in AxiLiteStatusType;
addr : in slv;
offset : in integer;
reg : in sl) return ()
- axiSlaveDefault ( signal axiWriteMaster : in AxiLiteWriteMasterType;
signal axiReadMaster : in AxiLiteReadMasterType;
variable axiWriteSlave : inout AxiLiteWriteSlaveType;
variable axiReadSlave : inout AxiLiteReadSlaveType;
variable axiStatus : in AxiLiteStatusType;
axiResp : in slv(1 downto 0) := AXI_RESP_OK_C;
extTxn : in sl := '0') return ()
- axiSlaveWaitTxn ( variable ep : inout AxiLiteEndpointType;
signal axiWriteMaster : in AxiLiteWriteMasterType;
signal axiReadMaster : in AxiLiteReadMasterType;
variable axiWriteSlave : in AxiLiteWriteSlaveType;
variable axiReadSlave : in AxiLiteReadSlaveType) return ()
Description
Simplified Address decode procedures, RTH 1/27/2016
- axiSlaveRegisterLegacy ( variable ep : inout AxiLiteEndpointType;
addr : in slv;
offset : in integer;
reg : inout slv;
constVal : in slv := "X") return ()
- axiSlaveRegister ( variable ep : inout AxiLiteEndpointType;
addr : in slv;
offset : in integer;
reg : inout slv;
constVal : in slv := "X") return ()
- axiSlaveRegisterR ( variable ep : inout AxiLiteEndpointType;
addr : in slv;
offset : in integer;
reg : in slv) return ()
- axiSlaveRegister ( variable ep : inout AxiLiteEndpointType;
addr : in slv;
offset : in integer;
reg : inout sl;
constVal : in sl := 'X') return ()
- axiSlaveRegisterR ( variable ep : inout AxiLiteEndpointType;
addr : in slv;
offset : in integer;
reg : in sl) return ()
- axiSlaveRegister ( variable ep : inout AxiLiteEndpointType;
addr : in slv;
regs : inout slv32Array) return ()
- axiSlaveRegisterR ( variable ep : inout AxiLiteEndpointType;
addr : in slv;
regs : in slv32Array) return ()
- axiWrDetect ( variable ep : inout AxiLiteEndpointType;
addr : in slv;
reg : inout sl) return ()
- axiRdDetect ( variable ep : inout AxiLiteEndpointType;
addr : in slv;
reg : inout sl) return ()
- axiSlaveDefault ( variable ep : inout AxiLiteEndpointType;
variable axiWriteSlave : inout AxiLiteWriteSlaveType;
variable axiReadSlave : inout AxiLiteReadSlaveType;
axiResp : in slv(1 downto 0) := AXI_RESP_OK_C;
extTxn : in sl := '0') return ()
- genAxiLiteConfig (num : positive;
base : slv(31 downto 0);
baseBot : integer range 1 to 32;
addrBits : integer range 0 to 31) return AxiLiteCrossbarMasterConfigArray
Description
Slave AXI Processing functions
Generate evenly distributed address map
- axiLiteBusSimWrite ( signal axilClk : in sl;
signal axilWriteMaster : out AxiLiteWriteMasterType;
signal axilWriteSlave : in AxiLiteWriteSlaveType;
addr : in slv(31 downto 0);
data : in slv;
debug : in boolean := false) return ()
Description
Simulation procedures
- axiLiteBusSimRead ( signal axilClk : in sl;
signal axilReadMaster : out AxiLiteReadMasterType;
signal axilReadSlave : in AxiLiteReadSlaveType;
addr : in slv(31 downto 0);
data : out slv;
debug : in boolean := false) return ()
- ite (i : boolean;
t : AxiLiteReadMasterType;
e : AxiLiteReadMasterType) return AxiLiteReadMasterType
- ite (i : boolean;
t : AxiLiteReadSlaveType;
e : AxiLiteReadSlaveType) return AxiLiteReadSlaveType
- ite (i : boolean;
t : AxiLiteWriteMasterType;
e : AxiLiteWriteMasterType) return AxiLiteWriteMasterType
- ite (i : boolean;
t : AxiLiteWriteSlaveType;
e : AxiLiteWriteSlaveType) return AxiLiteWriteSlaveType