Entity: AxiLiteSaciMasterTb
- File: AxiLiteSaciMasterTb.vhd
Diagram
Description
Title : SACI Protocol: https://confluence.slac.stanford.edu/x/YYcRDQ
Company : SLAC National Accelerator Laboratory
Description: Simulation testbed for AxiLiteSaciMaster2
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Signals
| Name | Type | Description |
|---|---|---|
| saciClk | sl | component ports |
| saciCmd | sl | |
| saciSelL | slv(SACI_NUM_CHIPS_G-1 downto 0) | |
| saciRsp | slv(ite(SACI_RSP_BUSSED_G, 0, SACI_NUM_CHIPS_G-1) downto 0) |
|
| axilClk | sl | |
| axilRst | sl | |
| axilRstL | sl | |
| axilReadMaster | AxiLiteReadMasterType | |
| axilReadSlave | AxiLiteReadSlaveType | |
| axilWriteMaster | AxiLiteWriteMasterType | |
| axilWriteSlave | AxiLiteWriteSlaveType | |
| rstLoopL | slv(SACI_NUM_CHIPS_G-1 downto 0) | |
| exec | slv(SACI_NUM_CHIPS_G-1 downto 0) | |
| ack | slv(SACI_NUM_CHIPS_G-1 downto 0) | |
| readL | slv(SACI_NUM_CHIPS_G-1 downto 0) | |
| cmd | slv7Array(SACI_NUM_CHIPS_G-1 downto 0) | |
| addr | slv12Array(SACI_NUM_CHIPS_G-1 downto 0) | |
| wrData | slv32Array(SACI_NUM_CHIPS_G-1 downto 0) | |
| rdData | slv32Array(SACI_NUM_CHIPS_G-1 downto 0) |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| TPD_G | time | 1 ns | |
| AXIL_CLK_PERIOD_G | real | 8.0e-9 | |
| AXIL_TIMEOUT_G | real | 1.0E-3 | |
| SACI_CLK_PERIOD_G | real | 1.0e-6 | |
| SACI_CLK_FREERUN_G | boolean | false | |
| SACI_NUM_CHIPS_G | positive range 1 to 4 | 4 | |
| SACI_RSP_BUSSED_G | boolean | false |
Processes
- AXIL: ( )
Instantiations
- U_AxiLiteSaciMaster2: surf.AxiLiteSaciMaster
- U_ClkRst_1: surf.ClkRst