Entity: AxiLiteSequencerRam
- File: AxiLiteSequencerRam.vhd
Diagram
Description
Company : SLAC National Accelerator Laboratory
Description: The slave AXI-Lite interface used to load a sequence of master AXI-Lite transactions. The transactions are stored in address=[1:2**ADDR_WIDTH_G-1]. Writing to Address[0] will start the transaction sequence and the number of transactions to execute. At the end of the sequence (or if a bus error is detected during the sequence) a slave AXI-lite bus response is executed. If there is a bus error, the address/response/data
is written into address[0] of the RAM for debugging.
Sequencer's RAM Address mapping: sAxil.address[0x00].BITADDR_WIDTH_G-1:0 = (r.size) Starts transactions and number of transactions to execute (zero exclusive) sAxil.address[0x00].BIT31:ADDR_WIDTH_G = Unused sAxil.address[0x04].BIT31:0 = Unused sAxil.address0x00 = zero if no error response else mAxil.Data[errorEvent].BIT[31:00] sAxil.address0x04 = zero if no error response else mAxil.Address[errorEvent].BIT[31:02] & errorResp sAxil.address[0x08] = Ram.Address[0x1].BIT[31:00]: Sequenced mAxil.Data[0].BIT[31:00] sAxil.address[0x0C] = Ram.Address[0x1].BIT[63:32]: Sequenced mAxil.Address[0].BIT[31:02] & '0' & RnW sAxil.address[0x10] = Ram.Address[0x2].BIT[31:00]: Sequenced mAxil.Data[1][31:00] sAxil.address[0x14] = Ram.Address[0x2].BIT[63:32]: Sequenced mAxil.Address[1].BIT[31:02] & '0' & RnW sAxil.address[0x18] = Ram.Address[0x3].BIT[31:00]: Sequenced mAxil.Data[2][31:00] sAxil.address[0x1C] = Ram.Address[0x3].BIT[63:32]: Sequenced mAxil.Address[2].BIT[31:02] & '0' & RnW ….. ….. sAxil.address[8r.size+0x0] = Ram.Address[r.size].BIT[31:00]: Sequenced mAxil.Data[r.size-1][31:00] sAxil.address[8r.size+0x4] = Ram.Address[r.size].BIT[63:32]: Sequenced mAxil.Address[r.size-1].BIT[31:02] & '0' & RnW
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Generics
| Generic name | Type | Value | Description |
|---|---|---|---|
| TPD_G | time | 1 ns | |
| SYNTH_MODE_G | string | "inferred" | |
| MEMORY_TYPE_G | string | "block" | |
| MEMORY_INIT_FILE_G | string | "none" | Used for MEMORY_TYPE_G="XPM only |
| MEMORY_INIT_PARAM_G | string | "0" | Used for MEMORY_TYPE_G="XPM only |
| WAIT_FOR_RESPONSE_G | boolean | false | false: immediately respond back for address[0], true: wait for the end of the transaction sequences |
| READ_LATENCY_G | natural range 0 to 3 | 2 | |
| ADDR_WIDTH_G | positive | 8 |
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| axilClk | in | sl | Clock and Reset |
| axilRst | in | sl | |
| extStart | in | sl | External Control Interface |
| extSize | in | slv(ADDR_WIDTH_G-1 downto 0) | |
| extBusy | out | sl | |
| extDone | out | sl | |
| sAxilReadMaster | in | AxiLiteReadMasterType | Slave AXI-Lite Interface |
| sAxilReadSlave | out | AxiLiteReadSlaveType | |
| sAxilWriteMaster | in | AxiLiteWriteMasterType | |
| sAxilWriteSlave | out | AxiLiteWriteSlaveType | |
| mAxilReadMaster | out | AxiLiteReadMasterType | Master AXI-Lite Interface |
| mAxilReadSlave | in | AxiLiteReadSlaveType | |
| mAxilWriteMaster | out | AxiLiteWriteMasterType | |
| mAxilWriteSlave | in | AxiLiteWriteSlaveType |
Signals
| Name | Type | Description |
|---|---|---|
| r | RegType | |
| rin | RegType | |
| seqData | slv(63 downto 0) | |
| dout | slv(63 downto 0) | |
| ack | AxiLiteAckType |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| AXI_RAM_ADDR_HIGH_C | integer | ADDR_WIDTH_G+AXI_DEC_ADDR_RANGE_C'high | |
| AXI_RAM_ADDR_LOW_C | integer | AXI_DEC_ADDR_RANGE_C'high+1 | |
| REG_INIT_C | RegType | ( extBusy => '0', extDone => '0', sAxilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, sAxilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, wstrb => (others => '0'), din => (others => '0'), addr => (others => '0'), size => (others => '0'), cnt => (others => '0'), seqAddr => (others => '0'), resp => (others => '0'), rdLatecy => 0, req => AXI_LITE_REQ_INIT_C, state => IDLE_S) |
Types
| Name | Type | Description |
|---|---|---|
| StateType | ( IDLE_S, S_AXI_RD_S, M_AXI_REQ_S, M_AXI_ACK_S, SEQ_DONE_S) |
|
| RegType |
Processes
- comb: ( ack, axilRst, dout, extSize, extStart, r, sAxilReadMaster,
sAxilWriteMaster, seqData )
- seq: ( axilClk )
Instantiations
- U_AxiLiteMaster: surf.AxiLiteMaster