Entity: AxiLiteSrpV0Tb
- File: AxiLiteSrpV0Tb.vhd
Diagram
Description
Company : SLAC National Accelerator Laboratory
Description: Simulation testbed for AxiLiteSrpV0
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Signals
| Name | Type | Description |
|---|---|---|
| axisClk | sl | [in] |
| axisRst | sl | [in] |
| txAxisMaster | AxiStreamMasterType | [out] |
| txAxisSlave | AxiStreamSlaveType | [in] |
| rxAxisMaster | AxiStreamMasterType | [in] |
| rxAxisSlave | AxiStreamSlaveType | [out] |
| rxAxisCtrl | AxiStreamCtrlType | [out] |
| axilClk | sl | [in] |
| axilRst | sl | [in] |
| uutAxilWriteMaster | AxiLiteWriteMasterType | [in] |
| uutAxilWriteSlave | AxiLiteWriteSlaveType | [out] |
| uutAxilReadMaster | AxiLiteReadMasterType | [in] |
| uutAxilReadSlave | AxiLiteReadSlaveType | [out] |
| srpAxilWriteMaster | AxiLiteWriteMasterType | [in] |
| srpAxilWriteSlave | AxiLiteWriteSlaveType | [out] |
| srpAxilReadMaster | AxiLiteReadMasterType | [in] |
| srpAxilReadSlave | AxiLiteReadSlaveType |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| TPD_G | time | 1 ns | |
| RESP_THOLD_G | integer range 0 to (2**24) | 1 | |
| SLAVE_READY_EN_G | boolean | true | |
| MEMORY_TYPE_G | string | "block" | |
| GEN_SYNC_FIFO_G | boolean | false | |
| FIFO_ADDR_WIDTH_G | integer range 4 to 48 | 9 | |
| FIFO_PAUSE_THRESH_G | integer range 1 to (2**24) | 2**8 | |
| AXI_STREAM_CONFIG_G | AxiStreamConfigType | EMAC_AXIS_CONFIG_C |
Processes
- test: ( )
Description
[out] ----------------------------------------------------------------------------------------------- Test process -----------------------------------------------------------------------------------------------
Instantiations
- U_ClkRst_AXIS: surf.ClkRst
- U_ClkRst_AXIL: surf.ClkRst
- U_AxiLiteSrpV0: surf.AxiLiteSrpV0
Description
Instantiate UUT
- U_SrpV0AxiLite_1: surf.SrpV0AxiLite
Description
[out]
Connect to SrpV0AxiLite
- U_AxiDualPortRam_1: surf.AxiDualPortRam
Description