Entity: AxiLiteWriteFilterTb
- File: AxiLiteWriteFilterTb.vhd
Diagram
Description
Company : SLAC National Accelerator Laboratory
Description: Testbench for design "AxiLiteAsync"
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Signals
| Name | Type | Description |
|---|---|---|
| axilReadMaster | AxiLiteReadMasterType | |
| axilReadSlave | AxiLiteReadSlaveType | |
| axilWriteMaster | AxiLiteWriteMasterType | |
| axilWriteSlave | AxiLiteWriteSlaveType | |
| filterWriteMaster | AxiLiteWriteMasterType | |
| filterWriteSlave | AxiLiteWriteSlaveType | |
| axilClk | sl | |
| axilRst | sl | |
| enFilter | sl | |
| blockAll | sl |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| CLK_PERIOD_C | time | 10 ns | |
| TPD_G | time | (CLK_PERIOD_C/4) |
Processes
- test: ( )
Instantiations
- U_axilClk: surf.ClkRst
- U_Filter: surf.AxiLiteWriteFilter
- U_Mem: surf.AxiDualPortRam