Entity: AxiMicronN25QReg
- File: AxiMicronN25QReg.vhd
Diagram
Description
Company : SLAC National Accelerator Laboratory
Description: MicronN25Q AXI-Lite Register Access
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Generics
| Generic name | Type | Value | Description |
|---|---|---|---|
| TPD_G | time | 1 ns | |
| EN_PASSWORD_LOCK_G | boolean | false | |
| PASSWORD_LOCK_G | slv(31 downto 0) | x"DEADBEEF" | |
| MEM_ADDR_MASK_G | slv(31 downto 0) | x"00000000" | |
| AXI_CLK_FREQ_G | real | 200.0E+6 | units of Hz |
| SPI_CLK_FREQ_G | real | 25.0E+6 |
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| csL | out | sl | FLASH Memory Ports |
| sck | out | sl | |
| mosi | out | sl | |
| miso | in | sl | |
| busyIn | in | sl | Shared SPI Interface |
| busyOut | out | sl | |
| axiReadMaster | in | AxiLiteReadMasterType | AXI-Lite Register Interface |
| axiReadSlave | out | AxiLiteReadSlaveType | |
| axiWriteMaster | in | AxiLiteWriteMasterType | |
| axiWriteSlave | out | AxiLiteWriteSlaveType | |
| axiClk | in | sl | Global Signals |
| axiRst | in | sl |
Signals
| Name | Type | Description |
|---|---|---|
| r | RegType | |
| rin | RegType | |
| ramDout | slv(7 downto 0) |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| DOUBLE_SCK_FREQ_C | real | SPI_CLK_FREQ_G * 2.0 | |
| SCK_HALF_PERIOD_C | natural | (getTimeRatio(AXI_CLK_FREQ_G, DOUBLE_SCK_FREQ_C))-1 |
|
| MIN_CS_WIDTH_C | natural | (getTimeRatio(AXI_CLK_FREQ_G, 2.0E+7)) |
|
| MAX_SCK_CNT_C | natural | ite((SCK_HALF_PERIOD_C > MIN_CS_WIDTH_C), SCK_HALF_PERIOD_C, MIN_CS_WIDTH_C) |
|
| PRESET_32BIT_ADDR_C | slv(8 downto 0) | "111111011" | |
| PRESET_24BIT_ADDR_C | slv(8 downto 0) | "111111100" | |
| REG_INIT_C | RegType | ( test => (others => '0'), wrData => (others => '0'), rdData => (others => '0'), addr => (others => '0'), addr32BitMode => '0', cmd => (others => '0'), status => (others => '0'), -- RAM Signals RnW => '1', we => '0', rd => "00", cnt => (others => '0'), waddr => (others => '0'), raddr => (others => '0'), xferSize => (others => '0'), ramDin => (others => '0'), -- SPI Signals busy => '0', csL => '1', sck => '0', mosi => '0', sckCnt => 0, bitPntr => 0, -- AXI-Lite Signals axiReadSlave => AXI_LITE_READ_SLAVE_INIT_C, axiWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, -- Status Machine state => IDLE_S) |
Types
| Name | Type | Description |
|---|---|---|
| StateType | ( IDLE_S, WORD_WRITE_S, WORD_READ_S, SCK_LOW_S, SCK_HIGH_S, MIN_CS_WIDTH_S) |
|
| RegType |
Processes
- comb: ( axiReadMaster, axiRst, axiWriteMaster, busyIn, miso, r,
ramDout )
- seq: ( axiClk )
Instantiations
- U_Ram: surf.SimpleDualPortRam