Entity: AxiRam

Diagram

time TPD_G string SYNTH_MODE_G string MEMORY_TYPE_G natural range 0 to 2 READ_LATENCY_G AxiConfigType AXI_CONFIG_G sl axiClk sl axiRst AxiWriteMasterType sAxiWriteMaster AxiReadMasterType sAxiReadMaster AxiWriteSlaveType sAxiWriteSlave AxiReadSlaveType sAxiReadSlave

Description

Company : SLAC National Accelerator Laboratory

Description: General AXI RAM Module

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Generics

Generic name Type Value Description
TPD_G time 1 ns
SYNTH_MODE_G string "inferred"
MEMORY_TYPE_G string "block"
READ_LATENCY_G natural range 0 to 2 2
AXI_CONFIG_G AxiConfigType

Ports

Port name Direction Type Description
axiClk in sl Clock and Reset
axiRst in sl
sAxiWriteMaster in AxiWriteMasterType Slave Write Interface
sAxiWriteSlave out AxiWriteSlaveType
sAxiReadMaster in AxiReadMasterType Slave Read Interface
sAxiReadSlave out AxiReadSlaveType

Signals

Name Type Description
r RegType
rin RegType
wrEn sl
wrData slv(DATA_WIDTH_C-1 downto 0)
wrAddr slv(ADDR_WIDTH_C-1 downto 0)
wstrb slv(DATA_BYTES_C-1 downto 0)
rdEn slv(1 downto 0)
rdData slv(DATA_WIDTH_C-1 downto 0)
rdAddr slv(ADDR_WIDTH_C-1 downto 0)

Constants

Name Type Value Description
DATA_BYTES_C positive AXI_CONFIG_G.DATA_BYTES_C
DATA_WIDTH_C positive 8*DATA_BYTES_C
OFFSET_C positive ite(DATA_BYTES_C = 1,
0,
log2(DATA_BYTES_C))
ADDR_WIDTH_C positive AXI_CONFIG_G.ADDR_WIDTH_C-OFFSET_C
REG_INIT_C RegType ( -- Write Signals wrData => (others => '0'),
wrAddr => (others => '0'),
wstrb => (others => '0'),
wid => (others => '0'),
awlen => (others => '0'),
sAxiWriteSlave => AXI_WRITE_SLAVE_INIT_C,
wrState => WR_ADDR_S,
-- Read Signals rdAddr => (others => '0'),
rid => (others => '0'),
arlen => (others => '0'),
sAxiReadSlave => AXI_READ_SLAVE_INIT_C,
rdEn => (others => '0'),
rdLat => (others => '0'),
rdState => RD_ADDR_S)

Types

Name Type Description
WrStateType ( WR_ADDR_S,
WR_DATA_S,
WR_BLOWOFF_S)
RdStateType ( RD_ADDR_S,
RD_PIPELINE_S,
RD_DATA_S)
RegType

Processes