Entity: AxiRateGen
- File: AxiRateGen.vhd
Diagram
Description
Company : SLAC National Accelerator Laboratory
Description: General Purpose AXI4 memory rate generator
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Generics
Generic name | Type | Value | Description |
---|---|---|---|
TPD_G | time | 1 ns | |
COMMON_CLK_G | boolean | false | |
AXI_CONFIG_G | AxiConfigType |
Ports
Port name | Direction | Type | Description |
---|---|---|---|
axiClk | in | sl | AXI4 Memory Interface |
axiRst | in | sl | |
axiWriteMaster | out | AxiWriteMasterType | |
axiWriteSlave | in | AxiWriteSlaveType | |
axiReadMaster | out | AxiReadMasterType | |
axiReadSlave | in | AxiReadSlaveType | |
axilClk | in | sl | AXI-Lite Interface |
axilRst | in | sl | |
sAxilReadMaster | in | AxiLiteReadMasterType | |
sAxilReadSlave | out | AxiLiteReadSlaveType | |
sAxilWriteMaster | in | AxiLiteWriteMasterType | |
sAxilWriteSlave | out | AxiLiteWriteSlaveType |
Signals
Name | Type | Description |
---|---|---|
r | RegType | |
rin | RegType | |
axilReadMaster | AxiLiteReadMasterType | |
axilReadSlave | AxiLiteReadSlaveType | |
axilWriteMaster | AxiLiteWriteMasterType | |
axilWriteSlave | AxiLiteWriteSlaveType |
Constants
Name | Type | Value | Description |
---|---|---|---|
REG_INIT_C | RegType | ( wrState => WRITE_ADDR_S, rdState => READ_ADDR_S, awlen => x"00", writeSize => x"FFF", wrTimer => x"0000_0000", rdTimer => x"0000_0000", -- Registers wrEnable => '0', rdEnable => '0', wrSize => x"FFF", rdSize => x"FFF", wrPeriod => x"0000_FFFF", rdPeriod => x"0000_FFFF", awburst => "01", awcache => "1111", arburst => "01", arcache => "1111", -- AXI4 axiWriteMaster => axiWriteMasterInit(AXI_CONFIG_G), axiReadMaster => axiReadMasterInit(AXI_CONFIG_G), -- AXI-Lite axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C) |
Types
Name | Type | Description |
---|---|---|
WrStateType | ( WRITE_ADDR_S, WRITE_DATA_S, WRITE_RESP_S) |
|
RdStateType | ( READ_ADDR_S, READ_DATA_S) |
|
RegType |
Processes
- comb: ( axiReadSlave, axiRst, axiWriteSlave, axilReadMaster,
axilWriteMaster, r )
- seq: ( axiClk )
Instantiations
- U_AxiLiteAsync: surf.AxiLiteAsync