Entity: AxiRssiCoreTb
- File: AxiRssiCoreTb.vhd
Diagram
Description
Title : RSSI Protocol: https://confluence.slac.stanford.edu/x/1IyfD
Company : SLAC National Accelerator Laboratory
Description: Simulation Testbed for testing the AxiRssiCore
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Signals
| Name | Type | Description |
|---|---|---|
| r | RegType | |
| rin | RegType | |
| clk | sl | |
| rst | sl | |
| txMaster | AxiStreamMasterType | |
| txSlave | AxiStreamSlaveType | |
| ibSrvMaster | AxiStreamMasterType | |
| ibSrvSlave | AxiStreamSlaveType | |
| obSrvMaster | AxiStreamMasterType | |
| obSrvSlave | AxiStreamSlaveType | |
| ibCltMaster | AxiStreamMasterType | |
| ibCltSlave | AxiStreamSlaveType | |
| obCltMaster | AxiStreamMasterType | |
| obCltSlave | AxiStreamSlaveType | |
| axiWriteMasters | AxiWriteMasterArray(3 downto 0) | |
| axiWriteSlaves | AxiWriteSlaveArray(3 downto 0) | |
| axiReadMasters | AxiReadMasterArray(3 downto 0) | |
| axiReadSlaves | AxiReadSlaveArray(3 downto 0) | |
| rxMaster | AxiStreamMasterType | |
| rxSlave | AxiStreamSlaveType | |
| linkUp | sl | |
| updatedResults | sl | |
| errorDet | sl | |
| rxBusy | sl | |
| txBusy | sl |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| CLK_PERIOD_C | time | 10 ns | 1 us makes it easy to count clock cycles in sim GUI |
| TPD_G | time | CLK_PERIOD_C/4 | |
| CLK_FREQUENCY_C | real | 100.0E+6 | In units of Hz |
| TIMEOUT_UNIT_C | real | 1.0E-6 | In units of seconds |
| ACK_TOUT_C | positive | 25 | unit depends on TIMEOUT_UNIT_G |
| RETRANS_TOUT_C | positive | 50 | unit depends on TIMEOUT_UNIT_G (Recommended >= MAX_NUM_OUTS_SEG_G*Data segment transmission time) |
| NULL_TOUT_C | positive | 200 | unit depends on TIMEOUT_UNIT_G (Recommended >= 4*RETRANS_TOUT_G) |
| MAX_RETRANS_CNT_C | positive | 3 | Counters |
| MAX_CUM_ACK_CNT_C | positive | 2 | |
| JUMBO_C | boolean | true | |
| AXI_CONFIG_C | AxiConfigType | ( ADDR_WIDTH_C => ite(JUMBO_C, 16, 13), -- (true=64kB buffer), (false=8kB buffer) DATA_BYTES_C => 8, -- 8 bytes = 64-bits ID_BITS_C => 2, LEN_BITS_C => ite(JUMBO_C, 8, 7)) |
|
| REG_INIT_C | RegType | ( packetLength => toSlv(0, 32), trig => '0', txBusy => '0', errorDet => '0') |
Types
| Name | Type | Description |
|---|---|---|
| RegType | (true=2kB bursting),(false=1kB bursting) |
Processes
- comb: ( errorDet, ibCltSlave, ibSrvSlave, linkUp, obCltMaster,
obSrvMaster, r, rst, txBusy )
- seq: ( clk )
Instantiations
- U_ClkRst: surf.ClkRst
- U_SsiPrbsTx: surf.SsiPrbsTx
Description
PRBS TX
- U_RssiServer: surf.AxiRssiCoreWrapper
Description
RSSI Server
- U_RssiClient: surf.AxiRssiCoreWrapper
Description
RSSI Client
- U_SsiPrbsRx: surf.SsiPrbsRx