Entity: AxiStreamDmaV2Desc

• File: AxiStreamDmaV2Desc.vhd

Diagram

Description

Generics

Generic name	Type	Value	Description
TPD_G	time	1 ns
CHAN_COUNT_G	integer range 1 to 16	1	Number of read & write DMA engines to support for each descriptor engine
AXIL_BASE_ADDR_G	slv(31 downto 0)	x"00000000"	Base address of descriptor registers & FIFOs
AXI_CONFIG_G	AxiConfigType		Configuration of AXI bus, must be 64 bits (or wider)
DESC_AWIDTH_G	integer range 4 to 32	12	Number of descriptor entries in write FIFO and return ring buffers
DESC_ARB_G	boolean	true	Choose between one-clock arbitration for return descriptors or count and check selection
DESC_SYNTH_MODE_G	string	"inferred"	Choose between infeered or xpm generated descriptor FIFOs
DESC_MEMORY_TYPE_G	string	"block"	Choose the type of resources for the descriptor FIFOs when DESC_SYNTH_MODE_G="xpm"

Ports

Port name	Direction	Type	Description
axiClk	in	sl	Clock/Reset
axiRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType	Local AXI Lite Bus
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
interrupt	out	sl	Additional signals
online	out	slv(CHAN_COUNT_G-1 downto 0)
acknowledge	out	slv(CHAN_COUNT_G-1 downto 0)
dmaWrDescReq	in	AxiWriteDmaDescReqArray(CHAN_COUNT_G-1 downto 0)	DMA write descriptor request, ack and return
dmaWrDescAck	out	AxiWriteDmaDescAckArray(CHAN_COUNT_G-1 downto 0)
dmaWrDescRet	in	AxiWriteDmaDescRetArray(CHAN_COUNT_G-1 downto 0)
dmaWrDescRetAck	out	slv(CHAN_COUNT_G-1 downto 0)
dmaRdDescReq	out	AxiReadDmaDescReqArray(CHAN_COUNT_G-1 downto 0)	DMA read descriptor request, ack and return
dmaRdDescAck	in	slv(CHAN_COUNT_G-1 downto 0)
dmaRdDescRet	in	AxiReadDmaDescRetArray(CHAN_COUNT_G-1 downto 0)
dmaRdDescRetAck	out	slv(CHAN_COUNT_G-1 downto 0)
axiRdCache	out	slv(3 downto 0)	Config
axiWrCache	out	slv(3 downto 0)
axiWriteMasters	out	AxiWriteMasterArray(CHAN_COUNT_G-1 downto 0)	AXI Interface
axiWriteSlaves	in	AxiWriteSlaveArray(CHAN_COUNT_G-1 downto 0)
buffGrpPause	out	slv(7 downto 0)	Buffer Group Pause

Signals

Name	Type	Description
r	RegType
rin	RegType
rdFifoValid	slv(RD_FIFO_CNT_C-1 downto 0)
rdFifoDout	slv(RD_FIFO_BITS_C-1 downto 0)
wrFifoValid	slv(WR_FIFO_CNT_C-1 downto 0)
wrFifoDout	slv(WR_FIFO_BITS_C-1 downto 0)
intSwAckEn	sl
intCompValid	sl
intDiffValid	sl
invalidCount	sl
diffCnt	slv(31 downto 0)
holdoffCompare	sl
idBuffCompare	slv(7 downto 0)

Constants

Name	Type	Value	Description
AXI_DESC_CONFIG_C	AxiConfigType	( ADDR_WIDTH_C => AXI_CONFIG_G.ADDR_WIDTH_C, DATA_BYTES_C => 16, -- Force 128b descriptor ID_BITS_C => AXI_CONFIG_G.ID_BITS_C, LEN_BITS_C => AXI_CONFIG_G.LEN_BITS_C)
CHAN_SIZE_C	integer	bitSize(CHAN_COUNT_G-1)
RET_COUNT_C	integer	CHAN_COUNT_G*2
RET_SIZE_C	integer	bitSize(RET_COUNT_C-1)
RD_FIFO_CNT_C	integer	4
RD_FIFO_BITS_C	integer	RD_FIFO_CNT_C * 32
WR_FIFO_CNT_C	integer	2
WR_FIFO_BITS_C	integer	WR_FIFO_CNT_C * 32
REG_INIT_C	RegType	( -- Write descriptor interface dmaWrDescAck => (others => AXI_WRITE_DMA_DESC_ACK_INIT_C), dmaWrDescRetAck => (others => '0'), -- Read descriptor interface dmaRdDescReq => (others => AXI_READ_DMA_DESC_REQ_INIT_C), dmaRdDescRetAck => (others => '0'), -- AXI-Lite Register Access axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, -- AXI4 Descriptor axiWriteMaster => axiWriteMasterInit(AXI_DESC_CONFIG_C, '1', "01", "0000"), -- Configuration wrBaseAddr => (others => '0'), rdBaseAddr => (others => '0'), maxSize => (others => '0'), contEn => '0', dropEn => '0', enable => '0', forceInt => '0', intEnable => '0', online => (others => '0'), acknowledge => (others => '0'), fifoReset => '1', intSwAckReq => '0', intAckCount => (others => '0'), descWrCache => (others => '0'), buffRdCache => (others => '0'), buffWrCache => (others => '0'), enableCnt => (others => '0'), idBuffThold => (others => (others => '0')), -- FIFOs fifoDin => (others => '0'), wrFifoWr => (others => '0'), rdFifoWr => (others => '0'), addrFifoSel => '0', wrFifoRd => '0', wrFifoValidDly => (others => '0'), wrAddrValid => '0', rdFifoRd => '0', rdFifoValidDly => (others => '0'), rdAddrValid => '0', -- Write Desc Request wrReqValid => '0', wrReqCnt => 0, wrReqNum => (others => '0'), wrReqAcks => (others => '0'), wrReqMissed => (others => '0'), -- Desc Return descRetList => (others => '0'), descState => IDLE_S, descRetCnt => 0, descRetNum => (others => '0'), descRetAcks => (others => '0'), wrIndex => (others => '0'), wrMemAddr => (others => '0'), rdIndex => (others => '0'), rdMemAddr => (others => '0'), intReqEn => '0', intReqCount => (others => '0'), interrupt => '0', intHoldoff => toSlv(10000, 16), -- ~20 kHz intHoldoffCount => (others => '0'), idBuffCount => (others => (others => '0')), idBuffInc => (others => '0'), idBuffDec => (others => '0'), buffGrpPause => (others => '0'))

Types

Name	Type	Description
DescStateType	( IDLE_S, WRITE_S, READ_S, WAIT_S)
RegType

Processes

• comb: ( axiRst, axiWriteSlaves, axilReadMaster, axilWriteMaster,
  diffCnt, dmaRdDescAck, dmaRdDescRet, dmaWrDescReq,
  dmaWrDescRet, holdoffCompare, idBuffCompare, intSwAckEn,
  invalidCount, r, rdFifoDout, rdFifoValid, wrFifoDout,
  wrFifoValid )

• seq: ( axiClk )

Instantiations

• U_invalidCount: surf.DspComparator

• U_diffCnt: surf.DspAddSub

• U_holdoffCompare: surf.DspComparator