Entity: AxiStreamDmaV2WriteMux

Diagram

time TPD_G AxiConfigType AXI_CONFIG_G boolean AXI_READY_EN_G sl axiClk sl axiRst AxiWriteMasterType dataWriteMaster AxiWriteMasterType descWriteMaster AxiWriteSlaveType mAxiWriteSlave AxiCtrlType mAxiWriteCtrl AxiWriteSlaveType dataWriteSlave AxiCtrlType dataWriteCtrl AxiWriteSlaveType descWriteSlave AxiWriteMasterType mAxiWriteMaster

Description

Company : SLAC National Accelerator Laboratory

Description: This MUX is used to make sure that the write descriptor is sent after the data is sent. Else the descriptor can get to the

software driver before the data received

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Generics

Generic name Type Value Description
TPD_G time 1 ns
AXI_CONFIG_G AxiConfigType
AXI_READY_EN_G boolean false

Ports

Port name Direction Type Description
axiClk in sl Clock and reset
axiRst in sl
dataWriteMaster in AxiWriteMasterType DMA Data Write Path
dataWriteSlave out AxiWriteSlaveType
dataWriteCtrl out AxiCtrlType
descWriteMaster in AxiWriteMasterType DMA Descriptor Write Path
descWriteSlave out AxiWriteSlaveType
mAxiWriteMaster out AxiWriteMasterType MUX Write Path
mAxiWriteSlave in AxiWriteSlaveType
mAxiWriteCtrl in AxiCtrlType

Signals

Name Type Description
r RegType
rin RegType

Constants

Name Type Value Description
REG_INIT_C RegType ( pause => '0',
armed => '0',
descSlave => AXI_WRITE_SLAVE_INIT_C,
dataSlave => AXI_WRITE_SLAVE_INIT_C,
descriptor => AXI_WRITE_MASTER_INIT_C,
master => AXI_WRITE_MASTER_INIT_C,
state => ADDR_S)

Types

Name Type Description
StateType ( ADDR_S,
DATA_S,
DESC_S)
RegType

Processes