Entity: AxiStreamPipelineTb

Diagram

Description

Company : SLAC National Accelerator Laboratory

Description: Simulation Testbed for testing the AxiStreamPipelineTb module

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Signals

Name Type Description
r RegType
rin RegType
mAxisMaster AxiStreamMasterType
mAxisSlave AxiStreamSlaveType
sAxisMaster AxiStreamMasterType
sAxisSlave AxiStreamSlaveType
clk sl
rst sl
passed sl
failed sl

Constants

Name Type Value Description
CLK_PERIOD_C time 4 ns
TPD_C time CLK_PERIOD_C/4
PIPE_STAGES_C natural 1
MAX_CNT_C slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0) resize(x"000000000000000019999997E241C000",
AXI_STREAM_MAX_TDATA_WIDTH_C)
PRBS_TAPS_C NaturalArray (0 => 31,
1 => 6,
2 => 2,
3 => 1)		 constant MAX_CNT_C : slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0) := resize(x"000000000000000000000000000000FF",AXI_STREAM_MAX_TDATA_WIDTH_C);
REG_INIT_C RegType ( passed => '0',
failed => '0',
wrPbrs => x"AE64B770",
wrSof => '1',
wrPkt => (others => '0'),
wrCnt => (others => '0'),
wrSize => (others => '0'),
rdPbrs => x"5E68B7E2",
rdSof => '1',
rdPkt => (others => '0'),
rdCnt => (others => '0'),
rdSize => (others => '0'),
sAxisMaster => AXI_STREAM_MASTER_INIT_C,
mAxisSlave => AXI_STREAM_SLAVE_INIT_C)

Types

Name Type Description
RegType

Processes

Instantiations

Description
AxiStreamPipeline (VHDL module to be tested)