Entity: AxiStreamScatterGather
- File: AxiStreamScatterGather.vhd
Diagram
Description
Company : SLAC National Accelerator Laboratory
Description: Takes 6 APV bursts with 128 channels of data each and
transforms them into 128 "MultiSamples" with 6 samples each.
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Generics
| Generic name | Type | Value | Description |
|---|---|---|---|
| TPD_G | time | 1 ns | |
| AXIS_SLAVE_FRAME_SIZE_G | integer | 129 | |
| SLAVE_AXIS_CONFIG_G | AxiStreamConfigType | ||
| MASTER_AXIS_CONFIG_G | AxiStreamConfigType |
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| axiClk | in | sl | Master system clock, 125Mhz |
| axiRst | in | sl | |
| axilReadMaster | in | AxiLiteReadMasterType | (optional) Axi Bus for status and debug |
| axilReadSlave | out | AxiLiteReadSlaveType | |
| axilWriteMaster | in | AxiLiteWriteMasterType | |
| axilWriteSlave | out | AxiLiteWriteSlaveType | |
| sAxisMaster | in | AxiStreamMasterType | Input data |
| sAxisSlave | out | AxiStreamSlaveType | |
| sAxisCtrl | out | AxiStreamCtrlType | |
| mAxisMaster | out | AxiStreamMasterType | longWordCount : out slv(7 downto 0); badWordCount : out slv(7 downto 0); longWords : out slv(15 downto 0); badWords : out slv(15 downto 0); Output data |
| mAxisSlave | in | AxiStreamSlaveType | |
| mAxisCtrl | in | AxiStreamCtrlType |
Signals
| Name | Type | Description |
|---|---|---|
| ram | RamType | |
| txRamRdData | slv(SLAVE_DATA_LENGTH_C-1 downto 0) | |
| txFifoRdData | sl | |
| txFifoValid | sl | |
| r | RegType | |
| rin | RegType | |
| sSsiMaster | SsiMasterType |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| SEQUENCE_LENGTH_C | integer | MASTER_AXIS_CONFIG_G.TDATA_BYTES_C/SLAVE_AXIS_CONFIG_G.TDATA_BYTES_C | |
| SLAVE_DATA_LENGTH_C | integer | SLAVE_AXIS_CONFIG_G.TDATA_BYTES_C*8 | |
| MASTER_DATA_LENGTH_C | integer | MASTER_AXIS_CONFIG_G.TDATA_BYTES_C*8 | |
| RAM_DEPTH_RAW_C | integer | AXIS_SLAVE_FRAME_SIZE_G * SEQUENCE_LENGTH_C * 2 | |
| RAM_ADDR_LENGTH_C | integer | bitSize(RAM_DEPTH_RAW_C) | |
| RAM_DEPTH_C | integer | 2**RAM_ADDR_LENGTH_C | |
| REG_INIT_C | RegType | ( rxRamWrEn => '0', rxRamWrData => (others => '0'), rxRamWrAddr => (others => '0'), rxSofAddr => (others => '0'), rxFifoWrEn => '0', rxWordCount => (others => '0'), rxFrameNumber => (others => '0'), rxError => '0', mSsiMaster => ssiMasterInit(MASTER_AXIS_CONFIG_G), txRamRdAddr => (others => '0'), txRamRdEn => '0', txFifoRdEn => '0', txWordCount => (others => '0'), txFrameNumber => (others => '0'), txSof => '1', axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, longWordCount => (others => '0'), badWordCount => (others => '0'), longWords => (others => '0'), badWords => (others => '0')) |
Types
| Name | Type | Description |
|---|---|---|
| RamType | ----------------------------------------------------------------------------------------------- RAM ----------------------------------------------------------------------------------------------- | |
| RegType | ------------------------------------------------------------------------------------------------ |
Processes
- ramProc: ( axiClk )
- comb: ( axiRst, axilReadMaster, axilWriteMaster, r, sSsiMaster, txFifoRdData,
txFifoValid, txRamRdData )
- sync: ( axiClk )
Instantiations
- StatusFifo: surf.Fifo