Entity: AxiXadcMinimumCore

Diagram

time TPD_G sl vPIn sl vNIn AxiLiteReadMasterType axiReadMaster AxiLiteWriteMasterType axiWriteMaster sl axiClk sl axiRst AxiLiteReadSlaveType axiReadSlave AxiLiteWriteSlaveType axiWriteSlave

Description


Company : SLAC National Accelerator Laboratory

Description: Example of a simple XADC IP core w/ AXI-Lite

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Generics

Generic name Type Value Description
TPD_G time 1 ns

Ports

Port name Direction Type Description
vPIn in sl XADC Ports
vNIn in sl
axiReadMaster in AxiLiteReadMasterType AXI-Lite Register Interface
axiReadSlave out AxiLiteReadSlaveType
axiWriteMaster in AxiLiteWriteMasterType
axiWriteSlave out AxiLiteWriteSlaveType
axiClk in sl Clocks and Resets
axiRst in sl

Signals

Name Type Description
axiRstL sl

Instantiations