Entity: AxiXcf128Reg

Diagram

time TPD_G real AXI_CLK_FREQ_G AxiLiteReadMasterType axiReadMaster AxiLiteWriteMasterType axiWriteMaster AxiXcf128StatusType status sl axiClk sl axiRst AxiLiteReadSlaveType axiReadSlave AxiLiteWriteSlaveType axiWriteSlave AxiXcf128ConfigType config

Description

Company : SLAC National Accelerator Laboratory

Description: AXI-Lite Register Access

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Generics

Generic name Type Value Description
TPD_G time 1 ns
AXI_CLK_FREQ_G real 200.0E+6

Ports

Port name Direction Type Description
axiReadMaster in AxiLiteReadMasterType AXI-Lite Register Interface
axiReadSlave out AxiLiteReadSlaveType
axiWriteMaster in AxiLiteWriteMasterType
axiWriteSlave out AxiLiteWriteSlaveType
status in AxiXcf128StatusType Register Inputs/Outputs
config out AxiXcf128ConfigType
axiClk in sl Global Signals
axiRst in sl

Signals

Name Type Description
r RegType
rin RegType

Constants

Name Type Value Description
MAX_CNT_C natural (getTimeRatio(AXI_CLK_FREQ_G,
10.0E+6))-1
REG_INIT_C RegType ( (others => '0'),
(others => (others => '0')),
'0',
0,
AXI_XCF128_CONFIG_INIT_C,
IDLE_S,
AXI_LITE_READ_SLAVE_INIT_C,
AXI_LITE_WRITE_SLAVE_INIT_C)

Types

Name Type Description
stateType ( IDLE_S,
CMD_LOW_S,
CMD_HIGH_S,
WAIT_S,
DATA_LOW_S,
DATA_HIGH_S)
RegType

Processes