Package: ClockManager7Pkg

• File: ClockManager7Pkg.vhd

Types

Functions

• makeClockManager7Cfg ( CLKIN_PERIOD_G : real := 10.0;
  -- Input period in ns );
  DIVCLK_DIVIDE_G : integer range 1 to 106 := 1;
  CLKFBOUT_MULT_F_G : real range 1.0 to 64.0 := 1.0;
  CLKFBOUT_MULT_G : integer range 2 to 64 := 5;
  CLKOUT0_DIVIDE_F_G : real range 1.0 to 128.0 := 1.0;
  CLKOUT0_DIVIDE_G : integer range 1 to 128 := 1;
  CLKOUT1_DIVIDE_G : integer range 1 to 128 := 1;
  CLKOUT2_DIVIDE_G : integer range 1 to 128 := 1;
  CLKOUT3_DIVIDE_G : integer range 1 to 128 := 1;
  CLKOUT4_DIVIDE_G : integer range 1 to 128 := 1;
  CLKOUT5_DIVIDE_G : integer range 1 to 128 := 1;
  CLKOUT6_DIVIDE_G : integer range 1 to 128 := 1;
  CLKOUT0_PHASE_G : real range -360.0 to 360.0 := 0.0;
  CLKOUT1_PHASE_G : real range -360.0 to 360.0 := 0.0;
  CLKOUT2_PHASE_G : real range -360.0 to 360.0 := 0.0;
  CLKOUT3_PHASE_G : real range -360.0 to 360.0 := 0.0;
  CLKOUT4_PHASE_G : real range -360.0 to 360.0 := 0.0;
  CLKOUT5_PHASE_G : real range -360.0 to 360.0 := 0.0;
  CLKOUT6_PHASE_G : real range -360.0 to 360.0 := 0.0;
  CLKOUT0_DUTY_CYCLE_G : real range 0.01 to 0.99 := 0.5;
  CLKOUT1_DUTY_CYCLE_G : real range 0.01 to 0.99 := 0.5;
  CLKOUT2_DUTY_CYCLE_G : real range 0.01 to 0.99 := 0.5;
  CLKOUT3_DUTY_CYCLE_G : real range 0.01 to 0.99 := 0.5;
  CLKOUT4_DUTY_CYCLE_G : real range 0.01 to 0.99 := 0.5;
  CLKOUT5_DUTY_CYCLE_G : real range 0.01 to 0.99 := 0.5;
  CLKOUT6_DUTY_CYCLE_G : real range 0.01 to 0.99 := 0.5;
  CLKOUT0_RST_HOLD_G : integer range 3 to positive'high := 3;
  CLKOUT1_RST_HOLD_G : integer range 3 to positive'high := 3;
  CLKOUT2_RST_HOLD_G : integer range 3 to positive'high := 3;
  CLKOUT3_RST_HOLD_G : integer range 3 to positive'high := 3;
  CLKOUT4_RST_HOLD_G : integer range 3 to positive'high := 3;
  CLKOUT5_RST_HOLD_G : integer range 3 to positive'high := 3;
  CLKOUT6_RST_HOLD_G : integer range 3 to positive'high := 3;
  CLKOUT0_RST_POLARITY_G : sl := '1';
  CLKOUT1_RST_POLARITY_G : sl := '1';
  CLKOUT2_RST_POLARITY_G : sl := '1';
  CLKOUT3_RST_POLARITY_G : sl := '1';
  CLKOUT4_RST_POLARITY_G : sl := '1';
  CLKOUT5_RST_POLARITY_G : sl := '1';
  CLKOUT6_RST_POLARITY_G : sl := '1') return ClockManager7CfgType

• ite (i : boolean;
  t : ClockManager7CfgType;
  e : ClockManager7CfgType) return ClockManager7CfgType

  DIVCLK_DIVIDE_G    : integer range 1 to 106;
  CLKFBOUT_MULT_F_G  : real range 1.0 to 64.0;
  CLKFBOUT_MULT_G    : integer range 2 to 64;
  CLKOUT0_DIVIDE_F_G : real range 1.0 to 128.0;
  CLKOUT0_DIVIDE_G   : integer range 1 to 128;
  CLKOUT1_DIVIDE_G   : integer range 1 to 128;
  CLKOUT2_DIVIDE_G   : integer range 1 to 128;
  CLKOUT3_DIVIDE_G   : integer range 1 to 128;
  CLKOUT4_DIVIDE_G   : integer range 1 to 128;
  CLKOUT5_DIVIDE_G   : integer range 1 to 128;
  CLKOUT6_DIVIDE_G   : integer range 1 to 128;