Entity: DeviceDnaUltraScaleTb
- File: DeviceDnaUltraScaleTb.vhd
Diagram
Description
Company : SLAC National Accelerator Laboratory
Description: Simulation Testbed for testing the DeviceDnaUltraScale
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Signals
Name | Type | Description |
---|---|---|
dnaValue | slv(95 downto 0) | |
dnaValid | sl | |
clk | sl | |
rst | sl | |
passed | sl | |
failed | sl |
Constants
Name | Type | Value | Description |
---|---|---|---|
CLK_PERIOD_C | time | 10 ns | 1 us makes it easy to count clock cycles in sim GUI |
TPD_G | time | CLK_PERIOD_C/4 | |
SIM_DNA_VALUE_C | slv(95 downto 0) | x"400200000139CA294D9041C5" |
Processes
- unnamed: ( clk )
- unnamed: ( failed, passed )
Instantiations
- U_ClkRst: surf.ClkRst
- U_DeviceDnaUltraScale: surf.DeviceDnaUltraScale