Entity: EthMacFastTb

Diagram

Description


Company : SLAC National Accelerator Laboratory

Description: Simulation Testbed for testing the EthMac module fast RX input

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Usage: Run for 10us, check rxMaster - all 3 packets have passed through Purpose: This TB checks the what happens when a packet arrives immediately after the previous one. It generates 3 packets directly to the RX XGMII interface. Delay between packets 1 and 2 is 3 clock cycles, and 0 between packets 2 and 3. Simulation is successful if all 3 packets are passed onto rxMaster stream.


Signals

Name Type Description
clk sl
rst sl
phyReady sl
txMaster AxiStreamMasterType
txSlave AxiStreamSlaveType
rxMaster AxiStreamMasterType
rxSlave AxiStreamSlaveType
ethStatus EthMacStatusType
ethConfig EthMacConfigType
phyRxD slv(63 downto 0)
phyRxC slv(7 downto 0)
phyTxD slv(63 downto 0)
phyTxC slv(7 downto 0)

Constants

Name Type Value Description
CLK_PERIOD_C time 10 ns
TPD_G time (CLK_PERIOD_C/4)

Processes

Instantiations

Description

Ethernet MAC core