Entity: GigEthGtyUltraScaleWrapper
File : GigEthGtyUltraScaleWrapper.vhd Diagram time TPD_G natural range 1 to 4 NUM_LANE_G natural INT_PIPE_STAGES_G natural PIPE_STAGES_G positive FIFO_ADDR_WIDTH_G string SYNTH_MODE_G string MEMORY_TYPE_G boolean JUMBO_G boolean PAUSE_EN_G boolean USE_GTREFCLK_G real CLKIN_PERIOD_G positive DIVCLK_DIVIDE_G real CLKFBOUT_MULT_F_G real CLKOUT0_DIVIDE_F_G boolean EN_AXI_REG_G AxiStreamConfigArray(3 downto 0) AXIS_CONFIG_G Slv48Array(NUM_LANE_G-1 downto 0) localMac slv(NUM_LANE_G-1 downto 0) dmaClk slv(NUM_LANE_G-1 downto 0) dmaRst AxiStreamSlaveArray(NUM_LANE_G-1 downto 0) dmaIbSlaves AxiStreamMasterArray(NUM_LANE_G-1 downto 0) dmaObMasters slv(NUM_LANE_G-1 downto 0) axiLiteClk slv(NUM_LANE_G-1 downto 0) axiLiteRst AxiLiteReadMasterArray(NUM_LANE_G-1 downto 0) axiLiteReadMasters AxiLiteWriteMasterArray(NUM_LANE_G-1 downto 0) axiLiteWriteMasters sl extRst slv(NUM_LANE_G-1 downto 0) sigDet sl gtRefClk sl gtClkP sl gtClkN slv(NUM_LANE_G-1 downto 0) gtTxPolarity slv(NUM_LANE_G-1 downto 0) gtRxPolarity slv(NUM_LANE_G-1 downto 0) gtRxP slv(NUM_LANE_G-1 downto 0) gtRxN AxiStreamMasterArray(NUM_LANE_G-1 downto 0) dmaIbMasters AxiStreamSlaveArray(NUM_LANE_G-1 downto 0) dmaObSlaves AxiLiteReadSlaveArray(NUM_LANE_G-1 downto 0) axiLiteReadSlaves AxiLiteWriteSlaveArray(NUM_LANE_G-1 downto 0) axiLiteWriteSlaves sl phyClk sl phyRst slv(NUM_LANE_G-1 downto 0) phyReady sl refClkOut sl refRstOut slv(NUM_LANE_G-1 downto 0) gtTxP slv(NUM_LANE_G-1 downto 0) gtTxN
Description Company : SLAC National Accelerator Laboratory Description: Gty Wrapper for 1000BASE-X Ethernet
Note: This module supports up to a MGT QUAD of 1GigE interfaces This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html . No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file. Generics
Generic name
Type
Value
Description
TPD_G
time
1 ns
NUM_LANE_G
natural range 1 to 4
1
INT_PIPE_STAGES_G
natural
1
MAC Configurations
PIPE_STAGES_G
natural
1
FIFO_ADDR_WIDTH_G
positive
12
single 4K UltraRAM
SYNTH_MODE_G
string
"xpm"
MEMORY_TYPE_G
string
"ultra"
JUMBO_G
boolean
true
PAUSE_EN_G
boolean
true
USE_GTREFCLK_G
boolean
false
FALSE: gtClkP/N, TRUE: gtRefClk
CLKIN_PERIOD_G
real
8.0
DIVCLK_DIVIDE_G
positive
1
CLKFBOUT_MULT_F_G
real
8.0
CLKOUT0_DIVIDE_F_G
real
8.0
EN_AXI_REG_G
boolean
false
AXI-Lite Configurations
AXIS_CONFIG_G
AxiStreamConfigArray(3 downto 0)
(others => EMAC_AXIS_CONFIG_C)
AXI Streaming Configurations
Ports
Port name
Direction
Type
Description
localMac
in
Slv48Array(NUM_LANE_G-1 downto 0)
Local Configurations
dmaClk
in
slv(NUM_LANE_G-1 downto 0)
Streaming DMA Interface
dmaRst
in
slv(NUM_LANE_G-1 downto 0)
dmaIbMasters
out
AxiStreamMasterArray(NUM_LANE_G-1 downto 0)
dmaIbSlaves
in
AxiStreamSlaveArray(NUM_LANE_G-1 downto 0)
dmaObMasters
in
AxiStreamMasterArray(NUM_LANE_G-1 downto 0)
dmaObSlaves
out
AxiStreamSlaveArray(NUM_LANE_G-1 downto 0)
axiLiteClk
in
slv(NUM_LANE_G-1 downto 0)
Slave AXI-Lite Interface
axiLiteRst
in
slv(NUM_LANE_G-1 downto 0)
axiLiteReadMasters
in
AxiLiteReadMasterArray(NUM_LANE_G-1 downto 0)
axiLiteReadSlaves
out
AxiLiteReadSlaveArray(NUM_LANE_G-1 downto 0)
axiLiteWriteMasters
in
AxiLiteWriteMasterArray(NUM_LANE_G-1 downto 0)
axiLiteWriteSlaves
out
AxiLiteWriteSlaveArray(NUM_LANE_G-1 downto 0)
extRst
in
sl
Misc. Signals
phyClk
out
sl
phyRst
out
sl
phyReady
out
slv(NUM_LANE_G-1 downto 0)
sigDet
in
slv(NUM_LANE_G-1 downto 0)
gtRefClk
in
sl
MGT Clock Port
gtClkP
in
sl
gtClkN
in
sl
refClkOut
out
sl
Copy of internal MMCM reference clock and Reset
refRstOut
out
sl
gtTxPolarity
in
slv(NUM_LANE_G-1 downto 0)
Switch Polarity of TxN/TxP, RxN/RxP
gtRxPolarity
in
slv(NUM_LANE_G-1 downto 0)
gtTxP
out
slv(NUM_LANE_G-1 downto 0)
MGT Ports
gtTxN
out
slv(NUM_LANE_G-1 downto 0)
gtRxP
in
slv(NUM_LANE_G-1 downto 0)
gtRxN
in
slv(NUM_LANE_G-1 downto 0)
Signals
Name
Type
Description
gtClk
sl
gtClkBufg
sl
refClk
sl
refRst
sl
sysClk125
sl
sysRst125
sl
sysClk62
sl
sysRst62
sl
Instantiations
Description Select the Reference Clock
PwrUpRst_Inst: surf.PwrUpRst
Description Power Up Reset
U_MMCM: surf.ClockManagerUltraScale
Description Clock Manager