Entity: Gth7AutoPhaseAligner

Diagram

string GT_TYPE STD_LOGIC STABLE_CLOCK STD_LOGIC RUN_PHALIGNMENT STD_LOGIC PHALIGNDONE STD_LOGIC DLYSRESETDONE STD_LOGIC RECCLKSTABLE STD_LOGIC PHASE_ALIGNMENT_DONE STD_LOGIC DLYSRESET

Description

//////////////////////////////////////////////////////////////////////////////// // _ // / /\/ / // // \ / Vendor: Xilinx // \ \ \/ Version : 2.5 // \ \ Application : 7 Series FPGAs Transceivers Wizard // / / Filename : gtwizard_v2_5_auto_phase_align.vhd // // /\ // \ \ / \ // __\/___\ // // Description : The logic below implements the procedure to do automatic phase-alignment on the 7-series GTX as described in ug476pdf, version 1.3, Chapters "Using the TX Phase Alignment to Bypass the TX Buffer" and "Using the RX Phase Alignment to Bypass the RX Elastic Buffer" Should the logic below differ from what is described in a later version of the user-guide, you are using an auto-alignment block, which is out of date and needs to be updated for safe operation.

Module gtwizard_v2_5_AUTO_PHASE_ALIGN Generated by Xilinx 7 Series FPGAs Transceivers Wizard

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Generics

Generic name Type Value Description
GT_TYPE string "GTX"

Ports

Port name Direction Type Description
STABLE_CLOCK in STD_LOGIC Stable Clock, either a stable clock from the PCB
RUN_PHALIGNMENT in STD_LOGIC Signal from the main Reset-FSM to run the auto phase-alignment procedure
PHASE_ALIGNMENT_DONE out STD_LOGIC Auto phase-alignment performed sucessfully
PHALIGNDONE in STD_LOGIC \ Phase-alignment signals from and to the
DLYSRESET out STD_LOGIC
DLYSRESETDONE in STD_LOGIC /
RECCLKSTABLE in STD_LOGIC /on the RX-side.

Signals

Name Type Description
phalign_state phase_align_auto_fsm
phaligndone_prev std_logic
phaligndone_ris_edge std_logic
count_phalign_edges integer range 0 to 3
phaligndone_sync std_logic
dlysresetdone_sync std_logic

Types

Name Type Description
phase_align_auto_fsm ( INIT,
WAIT_PHRST_DONE,
COUNT_PHALIGN_DONE,
PHALIGN_DONE )

Processes

Instantiations

State machines

state transitions cluster_phalign_state phalign_state INIT INIT WAIT_PHRST_DONE WAIT_PHRST_DONE INIT->WAIT_PHRST_DONE RUN_PHALIGNMENT = '1' and RECCLKSTABLE = '1'    COUNT_PHALIGN_DONE COUNT_PHALIGN_DONE WAIT_PHRST_DONE->COUNT_PHALIGN_DONE dlysresetdone_sync = '1'    PHALIGN_DONE PHALIGN_DONE COUNT_PHALIGN_DONE->PHALIGN_DONE (GT_TYPE = "GTX" and count_phalign_edges = 2) or ((GT_TYPE = "GTH" or GT_TYPE = "GTP") and phaligndone_ris_edge = '1')