Entity: Gth7RxRstSeq

Diagram

time TPD_G std_logic RST_IN std_logic GTRXRESET_IN std_logic RXPMARESETDONE std_logic DRPCLK std_logic_vector(15 downto 0) DRPDO std_logic DRPRDY std_logic GTRXRESET_OUT std_logic_vector(8 downto 0) DRPADDR std_logic_vector(15 downto 0) DRPDI std_logic DRPEN std_logic DRPWE std_logic DRP_OP_DONE

Description

_ / /\/ / // \ / Vendor: Xilinx \ \ \/ Version : 3.4 \ \ Application : 7 Series FPGAs Transceivers Wizard / / Filename : gtwizard_0_gtrxreset_seq.vhd // /\ \ \ / \ __\/___\

Module gtwizard_0_gtrxreset_seq Generated by Xilinx 7 Series FPGAs Transceivers Wizard

(c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.

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Generics

Generic name Type Value Description
TPD_G time 1 ns

Ports

Port name Direction Type Description
RST_IN in std_logic
GTRXRESET_IN in std_logic
RXPMARESETDONE in std_logic
GTRXRESET_OUT out std_logic
DRPCLK in std_logic
DRPADDR out std_logic_vector(8 downto 0)
DRPDO in std_logic_vector(15 downto 0)
DRPDI out std_logic_vector(15 downto 0)
DRPRDY in std_logic
DRPEN out std_logic
DRPWE out std_logic
DRP_OP_DONE out std_logic

Signals

Name Type Description
state state_type
next_state state_type
gtrxreset_s std_logic
gtrxreset_ss std_logic
rxpmaresetdone_ss std_logic
rxpmaresetdone_sss std_logic
rd_data std_logic_vector(15 downto 0)
next_rd_data std_logic_vector(15 downto 0)
original_rd_data std_logic_vector(15 downto 0)
pmarstdone_fall_edge std_logic
gtrxreset_i std_logic
flag std_logic
gtrxreset_o std_logic
drpen_o std_logic
drpwe_o std_logic
drpaddr_o std_logic_vector(8 downto 0)
drpdi_o std_logic_vector(15 downto 0)
drp_op_done_o std_logic
RST std_logic
GTRXRESET std_logic

Types

Name Type Description
state_type ( idle,
drp_rd,
wait_rd_data,
wr_16,
wait_wr_done1,
wait_pmareset,
wr_20,
wait_wr_done2)

Processes

Description
drives DRP interface and GTRXRESET_OUT

Instantiations