Entity: Gtp7TxRst

Diagram

time TPD_G boolean DYNAMIC_QPLL_G integer range 4 to 20 STABLE_CLOCK_PERIOD integer range 2 to 8 RETRY_COUNTER_BITWIDTH boolean TX_PLL0_USED std_logic_vector(1 downto 0) qPllTxSelect std_logic STABLE_CLOCK std_logic TXUSERCLK std_logic SOFT_RESET std_logic TXPMARESETDONE std_logic TXOUTCLK std_logic PLL0REFCLKLOST std_logic PLL1REFCLKLOST std_logic PLL0LOCK std_logic PLL1LOCK std_logic TXRESETDONE std_logic MMCM_LOCK std_logic PHALIGNMENT_DONE std_logic GTTXRESET std_logic MMCM_RESET std_logic PLL0_RESET std_logic PLL1_RESET std_logic TX_FSM_RESET_DONE std_logic TXUSERRDY std_logic RUN_PHALIGNMENT std_logic RESET_PHALIGNMENT std_logic_vector (RETRY_COUNTER_BITWIDTH-1 downto 0) RETRY_COUNTER

Description

////////////////////////////////////////////////////////////////////////////// _ / /\/ / // \ / Vendor: Xilinx \ \ \/ Version : 3.0 \ \ Application : 7 Series FPGAs Transceivers Wizard / / Filename :gtwizard_0_tx_startup_fsm.vhd // /\ \ \ / \ __\/___\

Description : This module performs TX reset and initialization.

Module gtwizard_0_tx_startup_fsm Generated by Xilinx 7 Series FPGAs Transceivers Wizard

(c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.

This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws.

DISCLAIMER This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

CRITICAL APPLICATIONS Xilinx products are not designed or intended to be fail- safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability.

THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.

Generics

Generic name Type Value Description
TPD_G time 1 ns
DYNAMIC_QPLL_G boolean false
STABLE_CLOCK_PERIOD integer range 4 to 20 8 Period of the stable clock driving this state-machine, unit is [ns]
RETRY_COUNTER_BITWIDTH integer range 2 to 8 8
TX_PLL0_USED boolean false the TX Reset FSMs must

Ports

Port name Direction Type Description
qPllTxSelect in std_logic_vector(1 downto 0)
STABLE_CLOCK in std_logic Stable Clock, either a stable clock from the PCB
TXUSERCLK in std_logic TXUSERCLK as used in the design
SOFT_RESET in std_logic User Reset, can be pulled any time
TXPMARESETDONE in std_logic
TXOUTCLK in std_logic
PLL0REFCLKLOST in std_logic PLL0 Reference-clock for the GT is lost
PLL1REFCLKLOST in std_logic PLL1 Reference-clock for the GT is lost
PLL0LOCK in std_logic Lock Detect from the PLL0 of the GT
PLL1LOCK in std_logic Lock Detect from the PLL1 of the GT
TXRESETDONE in std_logic
MMCM_LOCK in std_logic
GTTXRESET out std_logic
MMCM_RESET out std_logic
PLL0_RESET out std_logic Reset PLL0
PLL1_RESET out std_logic Reset PLL1
TX_FSM_RESET_DONE out std_logic Reset-sequence has sucessfully been finished.
TXUSERRDY out std_logic
RUN_PHALIGNMENT out std_logic
RESET_PHALIGNMENT out std_logic
PHALIGNMENT_DONE in std_logic
RETRY_COUNTER out std_logic_vector (RETRY_COUNTER_BITWIDTH-1 downto 0) Number of

Signals

Name Type Description
tx_state tx_rst_fsm_type
soft_reset_sync std_logic
init_wait_count integer range 0 to WAIT_MAX
init_wait_done std_logic
pll_reset_asserted std_logic
tx_fsm_reset_done_int std_logic
tx_fsm_reset_done_int_s2 std_logic
tx_fsm_reset_done_int_s3 std_logic
txresetdone_s2 std_logic
txresetdone_s3 std_logic
retry_counter_int integer range 0 to MAX_RETRIES
time_out_counter integer range 0 to WAIT_TIMEOUT_2ms
count_1us integer range 0 to WAIT_1us
reset_time_out std_logic
count_1us_done std_logic
time_out_2ms std_logic \Flags that the various time-out points
time_tlock_max std_logic
time_out_500us std_logic /
mmcm_lock_count integer range 0 to MMCM_LOCK_CNT_MAX-1
mmcm_lock_int std_logic
mmcm_lock_i std_logic
mmcm_lock_reclocked std_logic
run_phase_alignment_int std_logic
run_phase_alignment_int_s2 std_logic
run_phase_alignment_int_s3 std_logic
wait_bypass_count integer range 0 to MAX_WAIT_BYPASS-1
time_out_wait_bypass std_logic
time_out_wait_bypass_s2 std_logic
time_out_wait_bypass_s3 std_logic
txuserrdy_i std_logic
refclk_lost std_logic
gttxreset_i std_logic
txpmaresetdone_i std_logic
txpmaresetdone_sync std_logic
pll0lock_sync std_logic
pll1lock_sync std_logic
pll0lock_prev std_logic
pll1lock_prev std_logic
pll0lock_ris_edge std_logic
pll1lock_ris_edge std_logic

Constants

Name Type Value Description
MMCM_LOCK_CNT_MAX integer 1024
STARTUP_DELAY integer 500 AR43482: Transceiver needs to wait for 500 ns after configuration
WAIT_CYCLES integer STARTUP_DELAY / STABLE_CLOCK_PERIOD Number of Clock-Cycles to wait after configuration
WAIT_MAX integer WAIT_CYCLES + 10 500 ns plus some additional margin
WAIT_TIMEOUT_2ms integer 2000000 / STABLE_CLOCK_PERIOD 2 ms time-out
WAIT_TLOCK_MAX integer 100000 / STABLE_CLOCK_PERIOD 100 us time-out
WAIT_TIMEOUT_500us integer 500000 / STABLE_CLOCK_PERIOD 100 us time-out
WAIT_1us_cycles integer 1000 / STABLE_CLOCK_PERIOD 1 us time-out
WAIT_1us integer WAIT_1us_cycles+ 10 1us plus some additional margin
MAX_RETRIES integer 2**RETRY_COUNTER_BITWIDTH-1
MAX_WAIT_BYPASS integer 45824 110000 TXUSRCLK cycles is the max time for Multi lane designs

Types

Name Type Description
tx_rst_fsm_type ( INIT,
ASSERT_ALL_RESETS,
RELEASE_PLL_RESET,
RELEASE_MMCM_RESET,
WAIT_RESET_DONE,
DO_PHASE_ALIGNMENT,
RESET_FSM_DONE)

Processes

Description
FSM for resetting the GTX/GTH/GTP in the 7-series. ~~~~~~~~~~
Following steps are performed: 1) Only for GTX - After configuration wait for approximately 500 ns as specified in answer-record 43482 2) Assert all resets on the GT and on an MMCM potentially connected. After that wait until a reference-clock has been detected. 3) Release the reset to the GT and wait until the GT-PLL has locked. 4) Release the MMCM-reset and wait until the MMCM has signalled lock. Also signal to the RX-side which PLL has been reset. 5) Wait for the RESET_DONE-signal from the GT. 6) Signal to start the phase-alignment procedure and wait for it to finish. 7) Reset-sequence has successfully run through. Signal this to the rest of the design by asserting TX_FSM_RESET_DONE.

Instantiations

Description
Clock Domain Crossing

State machines

  • FSM for resetting the GTX/GTH/GTP in the 7-series.

~~~~~~~~~~

Following steps are performed:

1) Only for GTX - After configuration wait for approximately 500 ns as specified in

answer-record 43482

2) Assert all resets on the GT and on an MMCM potentially connected.

After that wait until a reference-clock has been detected.

3) Release the reset to the GT and wait until the GT-PLL has locked.

4) Release the MMCM-reset and wait until the MMCM has signalled lock.

Also signal to the RX-side which PLL has been reset.

5) Wait for the RESET_DONE-signal from the GT.

6) Signal to start the phase-alignment procedure and wait for it to

finish.

7) Reset-sequence has successfully run through. Signal this to the

rest of the design by asserting TX_FSM_RESET_DONE.
state transitions cluster_tx_state tx_state INIT INIT ASSERT_ALL_RESETS ASSERT_ALL_RESETS INIT->ASSERT_ALL_RESETS init_wait_done = '1'    RELEASE_PLL_RESET RELEASE_PLL_RESET ASSERT_ALL_RESETS->RELEASE_PLL_RESET ((qPllTxSelect = "00") and (PLL0REFCLKLOST = '0') and pll_reset_asserted = '1') or    ((qPllTxSelect /= "00") and (PLL1REFCLKLOST = '0') and pll_reset_asserted = '1')    ASSERT_ALL_RESETS->RELEASE_PLL_RESET (TX_PLL0_USED and (PLL0REFCLKLOST = '0') and pll_reset_asserted = '1') or    (not TX_PLL0_USED and (PLL1REFCLKLOST = '0') and pll_reset_asserted = '1')    not ()    RELEASE_PLL_RESET->ASSERT_ALL_RESETS time_out_2ms = '1'    RELEASE_MMCM_RESET RELEASE_MMCM_RESET RELEASE_PLL_RESET->RELEASE_MMCM_RESET ((qPllTxSelect = "00") and (pll0lock_ris_edge = '1')) or    ((qPllTxSelect /= "00") and (pll1lock_ris_edge = '1'))    RELEASE_PLL_RESET->RELEASE_MMCM_RESET (TX_PLL0_USED and (pll0lock_ris_edge = '1')) or    (not TX_PLL0_USED and (pll1lock_ris_edge = '1'))    not ()    RELEASE_MMCM_RESET->ASSERT_ALL_RESETS time_tlock_max = '1' and mmcm_lock_reclocked = '0' and reset_time_out = '0'    WAIT_RESET_DONE WAIT_RESET_DONE RELEASE_MMCM_RESET->WAIT_RESET_DONE mmcm_lock_reclocked = '1'    WAIT_RESET_DONE->ASSERT_ALL_RESETS time_out_500us = '1' and reset_time_out = '0'    DO_PHASE_ALIGNMENT DO_PHASE_ALIGNMENT WAIT_RESET_DONE->DO_PHASE_ALIGNMENT txresetdone_s3 = '1'    DO_PHASE_ALIGNMENT->ASSERT_ALL_RESETS time_out_wait_bypass_s3 = '1'    RESET_FSM_DONE RESET_FSM_DONE DO_PHASE_ALIGNMENT->RESET_FSM_DONE PHALIGNMENT_DONE = '1'