Entity: IpV4EngineRx
- File: IpV4EngineRx.vhd
Diagram
Description
Company : SLAC National Accelerator Laboratory
Description: IPv4 RX Engine Module
Note: IPv4 checksum checked in EthMac core
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Generics
| Generic name | Type | Value | Description |
|---|---|---|---|
| TPD_G | time | 1 ns | |
| SIM_ERROR_HALT_G | boolean | false | |
| PROTOCOL_SIZE_G | positive | 1 | |
| PROTOCOL_G | Slv8Array | (0 => UDP_C) | |
| VLAN_G | boolean | false |
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| ibIpv4Master | in | AxiStreamMasterType | Interface to Ethernet Frame MUX/DEMUX |
| ibIpv4Slave | out | AxiStreamSlaveType | |
| localhostMaster | in | AxiStreamMasterType | |
| localhostSlave | out | AxiStreamSlaveType | |
| ibProtocolMasters | out | AxiStreamMasterArray(PROTOCOL_SIZE_G-1 downto 0) | Interface to Protocol Engine |
| ibProtocolSlaves | in | AxiStreamSlaveArray(PROTOCOL_SIZE_G-1 downto 0) | |
| clk | in | sl | Clock and Reset |
| rst | in | sl |
Signals
| Name | Type | Description |
|---|---|---|
| r | RegType | |
| rin | RegType | |
| rxMaster | AxiStreamMasterType | |
| rxSlave | AxiStreamSlaveType | |
| txSlave | AxiStreamSlaveType |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| REG_INIT_C | RegType | ( tLast => '0', eofe => '0', len => (others => '0'), protocol => (others => '0'), tKeep => (others => '0'), tData => (others => '0'), rxSlave => AXI_STREAM_SLAVE_INIT_C, txMaster => AXI_STREAM_MASTER_INIT_C, state => IDLE_S) |
Types
| Name | Type | Description |
|---|---|---|
| StateType | ( IDLE_S, IPV4_HDR0_S, IPV4_HDR1_S, IPV4_HDR2_S, MOVE_S, LAST_S) |
|
| RegType |
Processes
- comb: ( r, rst, rxMaster, txSlave )
- seq: ( clk )
Instantiations
- U_Mux: surf.AxiStreamMux
- U_AxisMux: surf.AxiStreamDeMux