Entity: Pgp2bGtx7VarLatWrapperTb

Diagram

Description


Title : PGPv2b: https://confluence.slac.stanford.edu/x/q86fD

Company : SLAC National Accelerator Laboratory

Description: Simulation Testbed for Pgp2bGtx7VarLatWrapper

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.


Signals

Name Type Description
extRst sl [in]
pgpClk sl [out]
pgpRst sl [out]
stableClk sl [out]
pgpTxIn Pgp2bTxInType [in]
pgpTxOut Pgp2bTxOutType [out]
pgpRxIn Pgp2bRxInType [in]
pgpRxOut Pgp2bRxOutType [out]
pgpTxMasters AxiStreamMasterArray(3 downto 0) [in]
pgpTxSlaves AxiStreamSlaveArray(3 downto 0) [out]
pgpRxMasters AxiStreamMasterArray(3 downto 0) [out]
pgpRxCtrl AxiStreamCtrlArray(3 downto 0) [in]
gtClkP sl [in]
gtClkN sl [in]
gtTxP sl [out]
gtTxN sl [out]
gtRxP sl [in]
gtRxN sl [in]
txPreCursor slv(4 downto 0) [in]
txPostCursor slv(4 downto 0) [in]
txDiffCtrl slv(3 downto 0) [in]
axilClk sl [in]
axilRst sl [in]
axilReadMaster AxiLiteReadMasterType [in]
axilReadSlave AxiLiteReadSlaveType [out]
axilWriteMaster AxiLiteWriteMasterType [in]
axilWriteSlave AxiLiteWriteSlaveType

Constants

Name Type Value Description
TPD_G time 1 ns
CLKIN_PERIOD_G real 16.0
DIVCLK_DIVIDE_G natural range 1 to 106 2
CLKFBOUT_MULT_F_G real range 1.0 to 64.0 31.875
CLKOUT0_DIVIDE_F_G real range 1.0 to 128.0 6.375
CPLL_REFCLK_SEL_G bit_vector "001"
CPLL_FBDIV_G natural 5
CPLL_FBDIV_45_G natural 5
CPLL_REFCLK_DIV_G natural 1
RXOUT_DIV_G natural 2
TXOUT_DIV_G natural 2
RX_CLK25_DIV_G natural 5
TX_CLK25_DIV_G natural 5
RX_OS_CFG_G bit_vector "0000010000000"
RXCDR_CFG_G bit_vector x"03000023ff40200020"
RXDFEXYDEN_G sl '1'
RX_DFE_KL_CFG2_G bit_vector x"301148AC"
TX_BUF_EN_G boolean true
TX_OUTCLK_SRC_G string "OUTCLKPMA"
TX_DLY_BYPASS_G sl '1'
TX_PHASE_ALIGN_G string "NONE"
VC_INTERLEAVE_G integer 0
PAYLOAD_CNT_TOP_G integer 7
NUM_VC_EN_G integer range 1 to 4 4
TX_ENABLE_G boolean true
RX_ENABLE_G boolean true

Instantiations