This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Generics
Generic name
Type
Value
Description
TPD_G
time
1 ns
INT_PIPE_STAGES_G
natural
0
PIPE_STAGES_G
natural
1
VALID_THOLD_G
positive
1
VALID_BURST_MODE_G
boolean
false
SYNTH_MODE_G
string
"inferred"
MEMORY_TYPE_G
string
"block"
GEN_SYNC_FIFO_G
boolean
false
FIFO_ADDR_WIDTH_G
positive
9
APP_AXI_CONFIG_G
AxiStreamConfigType
PHY_AXI_CONFIG_G
AxiStreamConfigType
Ports
Port name
Direction
Type
Description
axisClk
in
sl
AXIS Interface (axisClk domain)
axisRst
in
sl
axisMaster
in
AxiStreamMasterType
axisSlave
out
AxiStreamSlaveType
pgpClk
in
sl
PGP Interface (pgpClk domain)
pgpRst
in
sl
rxlinkReady
in
sl
txlinkReady
in
sl
pgpTxMaster
out
AxiStreamMasterType
pgpTxSlave
in
AxiStreamSlaveType
Signals
Name
Type
Description
sMaster
AxiStreamMasterType
sSlave
AxiStreamSlaveType
master
AxiStreamMasterType
ctrl
AxiStreamCtrlType
linkReady
sl
flushEn
sl
axisReset
sl
pgpReset
sl
Instantiations
U_FlushSync: surf.Synchronizer
U_axisRst: surf.RstPipeline
U_pgpRst: surf.RstPipeline
U_AxiStreamPipeline: surf.AxiStreamPipeline
Description
Adding Pipelining to help with making timing between SLRs