Entity: RssiCoreTb
- File: RssiCoreTb.vhd
Diagram
Description
Title : RSSI Protocol: https://confluence.slac.stanford.edu/x/1IyfD
Company : SLAC National Accelerator Laboratory
Description: Simulation Testbed for testing the RssiCore
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Signals
| Name | Type | Description |
|---|---|---|
| r | RegType | |
| rin | RegType | |
| clk | sl | |
| rst | sl | |
| axilWriteMasters | AxiLiteWriteMasterArray(NUM_XBAR_C-1 downto 0) | |
| axilWriteSlaves | AxiLiteWriteSlaveArray(NUM_XBAR_C-1 downto 0) | |
| axilReadMasters | AxiLiteReadMasterArray(NUM_XBAR_C-1 downto 0) | |
| axilReadSlaves | AxiLiteReadSlaveArray(NUM_XBAR_C-1 downto 0) | |
| sSrpMaster | AxiStreamMasterType | |
| sSrpSlave | AxiStreamSlaveType | |
| mSrpMaster | AxiStreamMasterType | |
| mSrpSlave | AxiStreamSlaveType | |
| tspMasters | AxiStreamMasterArray(1 downto 0) | |
| tspSlaves | AxiStreamSlaveArray(1 downto 0) | |
| txMaster | AxiStreamMasterType | |
| txSlave | AxiStreamSlaveType | |
| rxMaster | AxiStreamMasterType | |
| rxSlave | AxiStreamSlaveType | |
| statusReg | slv(6 downto 0) |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| CLK_PERIOD_C | time | 10 ns | 1 us makes it easy to count clock cycles in sim GUI |
| TPD_G | time | CLK_PERIOD_C/4 | |
| AXIS_CONFIG_C | AxiStreamConfigType | ssiAxiStreamConfig(4) | |
| AXIL_CONFIG_C | AxiLiteCrossbarMasterConfigArray(0 downto 0) | ( 0 => ( baseAddr => x"0000_0000", addrBits => 32, connectivity => x"FFFF")) |
|
| MAX_CNT_C | positive | (4096/4) | Up to 4kB writes and 4B per word |
| SWEEP_C | boolean | true | |
| APP_ILEAVE_EN_C | boolean | true | |
| REG_INIT_C | RegType | ( tid => x"0000_0000", cnt => x"0000_0000", sweep => x"0000_0000", txMaster => AXI_STREAM_MASTER_INIT_C, state => IDLE_S) |
|
| NUM_XBAR_C | positive | 8 |
Types
| Name | Type | Description |
|---|---|---|
| StateType | ( IDLE_S, HDR0_S, HDR1_S, HDR2_S, HDR3_S, HDR4_S, PAYLOAD_S) |
|
| RegType |
Processes
- comb: ( r, rst, statusReg, txSlave )
- seq: ( clk )
Instantiations
- U_ClkRst: surf.ClkRst
- U_SRPv3: surf.SrpV3AxiLite
Description
SRPv3 End Point
- U_RssiServer: surf.RssiCoreWrapper
Description
RSSI Server
- U_RssiClient: surf.RssiCoreWrapper