Entity: SgmiiDp83867Mdio

Diagram

time TPD_G natural range 1 to natural'high DIV_G natural range 0 to 15 PHY_G sl clk sl rst sl mdi sl linkIrq sl initDone sl speed_is_10_100 sl speed_is_100 sl linkIsUp sl mdc sl mdo

Description

Company : SLAC National Accelerator Laboratory

Description: Controller for the TI DP83867DP83867 ETH PHY

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Generics

Generic name Type Value Description
TPD_G time 1 ns
DIV_G natural range 1 to natural'high 1 half-period of MDC in clk cycles
PHY_G natural range 0 to 15 3

Ports

Port name Direction Type Description
clk in sl clock and reset
rst in sl
initDone out sl misc
speed_is_10_100 out sl
speed_is_100 out sl
linkIsUp out sl
mdc out sl MDIO interface
mdo out sl
mdi in sl
linkIrq in sl link status change interrupt

Signals

Name Type Description
r RegType
rin RegType
hdlrDone sl
args Slv16Array(0 to NUM_READ_ARGS_C - 1)

Constants

Name Type Value Description
P_INIT_C MdioProgramArray ( mdioWriteInst(PHY_G,
16#0D#,
x"001F",
false),
-- Address 0x000D: Setup for extended address mdioWriteInst(PHY_G,
16#0E#,
x"00D3",
false),
-- Address 0x000E: Set extended address = 0x00D3 mdioWriteInst(PHY_G,
16#0D#,
x"401F",
false),
-- Address 0x000D: Setup for extended data write mdioWriteInst(PHY_G,
16#0E#,
x"4000",
false),
-- Address 0x000E: Enable SGMII clock mdioWriteInst(PHY_G,
16#0D#,
x"001F",
false),
-- Address 0x000D: Setup for extended address mdioWriteInst(PHY_G,
16#0E#,
x"0032",
false),
-- Address 0x000E: Set extended address = 0x0032 mdioWriteInst(PHY_G,
16#0D#,
x"401F",
false),
-- Address 0x000D: Setup for extended data write mdioWriteInst(PHY_G,
16#0E#,
x"0000",
false),
-- Address 0x000E: RGMII must be disabled mdioWriteInst(PHY_G,
16#1E#,
x"0082",
false),
-- Address 0x001E: INTN/PWDNN Pad is an Interrupt Output. mdioWriteInst(PHY_G,
16#14#,
x"29C7",
false),
-- Address 0x0014: Configure interrupt polarity,
enable auto negotiation,
Enable Speed Optimization mdioWriteInst(PHY_G,
16#12#,
X"0c00",
false),
-- Address 0x0012: Interrupt of link and autoneg changes mdioWriteInst(PHY_G,
16#10#,
x"5868",
false),
-- Address 0x0010: Enable SGMII -- mdioWriteInst(PHY_G,
16#09#,
X"0200",
false),
-- Address 0x0009: Advertise 1000 FD only -- mdioWriteInst(PHY_G,
16#04#,
X"0140",
false),
-- Address 0x0004: Advertise 10/100 FD only mdioWriteInst(PHY_G,
16#00#,
x"1140",
false),
-- Address 0x0000: Enable autoneg and full duplex mdioWriteInst(PHY_G,
16#1F#,
x"4000",
true))
REG0x13_IDX_C natural 0 Address 0x001F: Initiate the soft restart.
REG0x11_IDX_C natural 1
P_HDLR_C MdioProgramArray ( REG0x13_IDX_C => mdioReadInst(PHY_G,
16#13#,
false),
-- read/ack/clear interrupt REG0x11_IDX_C => mdioReadInst(PHY_G,
16#11#,
true) -- read current speed and link status )		 IRQ Handler sequence: 1) read back and clear interrupts (reading does clear them) 2) obtain current link status and speed
NUM_READ_ARGS_C natural mdioProgNumReadTransactions(P_HDLR_C)
REG_INIT_C RegType ( s10_100 => '0',
s100 => '0',
linkIsUp => '0' )

Types

Name Type Description
RegType

Processes

Instantiations