Entity: Si5345
- File: Si5345.vhd
Diagram
Description
Company : SLAC National Accelerator Laboratory
Description: SPI Master Wrapper that includes a state machine for SPI paging
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Generics
| Generic name | Type | Value | Description |
|---|---|---|---|
| TPD_G | time | 1 ns | |
| MEMORY_INIT_FILE_G | string | "none" | Used to initialization boot ROM |
| CLK_PERIOD_G | real | (1.0/156.25E+6) | |
| SPI_SCLK_PERIOD_G | real | (1.0/10.0E+6) |
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| axiClk | in | sl | Clock and Reset |
| axiRst | in | sl | |
| axiReadMaster | in | AxiLiteReadMasterType | AXI-Lite Interface |
| axiReadSlave | out | AxiLiteReadSlaveType | |
| axiWriteMaster | in | AxiLiteWriteMasterType | |
| axiWriteSlave | out | AxiLiteWriteSlaveType | |
| booting | out | sl | Status Interface |
| coreRst | out | sl | SPI Interface |
| coreSclk | out | sl | |
| coreSDin | in | sl | |
| coreSDout | out | sl | |
| coreCsb | out | sl |
Signals
| Name | Type | Description |
|---|---|---|
| r | RegType | |
| rin | RegType | |
| freeRunClk | sl | |
| rdEn | sl | |
| rdData | slv(15 downto 0) | |
| ramData | slv(19 downto 0) |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| BOOT_ROM_C | boolean | (MEMORY_INIT_FILE_G /= "none") | |
| DLY_C | natural | 4*integer(SPI_SCLK_PERIOD_G/CLK_PERIOD_G) | >= 2 SCLK delay between SPI cycles |
| REG_INIT_C | RegType | ( axiRd => '0', wrEn => '0', wrData => (others => '0'), data => (others => '0'), addr => (others => '0'), page => (others => '0'), timer => 0, cnt => 0, wrArray => (others => (others => '0')), axiWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, axiReadSlave => AXI_LITE_READ_SLAVE_INIT_C, ramAddr => (others => '0'), booting => ite(BOOT_ROM_C, '1', '0'), state => BOOT_ROM_S) |
Types
| Name | Type | Description |
|---|---|---|
| StateType | ( BOOT_ROM_S, IDLE_S, INIT_S, REQ_S, ACK_S, DONE_S) |
|
| RegType |
Processes
- comb: ( axiReadMaster, axiRst, axiWriteMaster, r, ramData, rdData,
rdEn )
- seq: ( axiClk )
Instantiations
- U_SpiMaster: surf.SpiMaster