Entity: SlvArraytoAxiLite

Diagram

time TPD_G boolean COMMON_CLK_G positive SIZE_G Slv32Array ADDR_G sl clk sl rst Slv32Array(SIZE_G-1 downto 0) input sl axilClk sl axilRst AxiLiteReadSlaveType axilReadSlave AxiLiteWriteSlaveType axilWriteSlave AxiLiteReadMasterType axilReadMaster AxiLiteWriteMasterType axilWriteMaster

Description

Company : SLAC National Accelerator Laboratory

Description: SLV array to AXI-Lite Master Bridge

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Generics

Generic name Type Value Description
TPD_G time 1 ns
COMMON_CLK_G boolean false Set true if axilClk = clk
SIZE_G positive 1
ADDR_G Slv32Array (0 => x"00000000")

Ports

Port name Direction Type Description
clk in sl SLV Array Interface
rst in sl
input in Slv32Array(SIZE_G-1 downto 0)
axilClk in sl AXI-Lite Master Interface
axilRst in sl
axilReadMaster out AxiLiteReadMasterType
axilReadSlave in AxiLiteReadSlaveType
axilWriteMaster out AxiLiteWriteMasterType
axilWriteSlave in AxiLiteWriteSlaveType

Signals

Name Type Description
r RegType
rin RegType
inSlv Slv32Array(SIZE_G-1 downto 0)
ack AxiLiteAckType

Constants

Name Type Value Description
REG_INIT_C RegType ( cnt => 0,
valid => (others => '0'),
inSlv => (others => (others => '0')),
req => AXI_LITE_REQ_INIT_C,
state => IDLE_S)

Types

Name Type Description
StateType ( IDLE_S,
WAIT_S)
RegType

Processes

Instantiations