Entity: SlvDelayRamTb

Diagram

Description


Company : SLAC National Accelerator Laboratory

Description: Simulation Testbed for the SlvDelayRam module

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Signals

Name Type Description
r RegType
rin RegType
clk sl
rst sl
din slv(WIDTH_C - 1 downto 0)
dout slv(WIDTH_C - 1 downto 0)
maxCount slv(MAX_COUNT_BITS_C - 1 downto 0)
passed sl
failed sl

Constants

Name Type Value Description
CLK_PERIOD_C time 4 ns
TPD_C time CLK_PERIOD_C/4
WIDTH_C integer 16
MAX_DELAY_C integer 514
DELAY_C integer MAX_DELAY_C
DO_REG_C boolean true
MEMORY_TYPE_C string "block"
MAX_COUNT_BITS_C integer log2(MAX_DELAY_C - ite(DO_REG_C,
2,
1))
may save a bit if MAX_DELAY is just over pow2 ex 514 elements only needs 9 bits
MAX_COUNT_C integer DELAY_C - ite(DO_REG_C,
3,
2)
delay = maxCount + ite(DO_REG_G, 3, 2);
REG_INIT_C RegType ( passed => '0',
failed => '0',
count => 0,
countDelay => (others => 0))

Types

Name Type Description
countDelayType
RegType

Processes

Description
----------------------------------------------- FSM to sweep through all possible combination ----------------------------------------------

Instantiations

Description

Module to be testing