Description: Shift Register Delay module for std_logic_vector Uses a counter and single port RAM (distributed, block, ultra) Single port RAM setup in read first mode Counter counts 0…maxCount Optional data out register (DO_REG_G) on the RAM
delay = maxCount + ite(DO_REG_G, 3, 2)
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the terms contained in the LICENSE.txt file.
Generics
Generic name
Type
Value
Description
TPD_G
time
1 ns
XIL_DEVICE_G
string
"ULTRASCALE_PLUS"
DELAY_STYLE_G
string
"srl_reg"
"reg", "srl", "srl_reg", "reg_srl", "reg_srl_reg" or "block"