Entity: Srl16Delay

Diagram

time TPD_G string XIL_DEVICE_G natural range 3 to 17 DELAY_G positive WIDTH_G sl clk slv(WIDTH_G-1 downto 0) din slv(3 downto 0) dly_2 slv(WIDTH_G-1 downto 0) dout

Description

Company : SLAC National Accelerator Laboratory

Description: SRL16 delay module - pack 2 SRL16 per slice

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Generics

Generic name Type Value Description
TPD_G time 1 ns
XIL_DEVICE_G string "ULTRASCALE_PLUS" "7SERIES" or "ULTRASCALE" or "ULTRASCALE_PLUS"
DELAY_G natural range 3 to 17 3 default number of clock cycle delays
WIDTH_G positive 16

Ports

Port name Direction Type Description
clk in sl
din in slv(WIDTH_G-1 downto 0)
dout out slv(WIDTH_G-1 downto 0)
dly_2 in slv(3 downto 0)

Signals

Name Type Description
q slv(WIDTH_G-1 downto 0)

Processes