Entity: SrpV3AxiLiteTb
- File: SrpV3AxiLiteTb.vhd
Diagram
Description
Company : SLAC National Accelerator Laboratory
Description: Simulation testbed for SrpV3AxiLite
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Signals
| Name | Type | Description |
|---|---|---|
| r | RegType | |
| rin | RegType | |
| clk | sl | |
| rst | sl | |
| axilWriteMaster | AxiLiteWriteMasterType | |
| axilWriteSlave | AxiLiteWriteSlaveType | |
| axilReadMaster | AxiLiteReadMasterType | |
| axilReadSlave | AxiLiteReadSlaveType | |
| axilWriteMasters | AxiLiteWriteMasterArray(NUM_AXIL_MASTERS_C-1 downto 0) | |
| axilWriteSlaves | AxiLiteWriteSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) | |
| axilReadMasters | AxiLiteReadMasterArray(NUM_AXIL_MASTERS_C-1 downto 0) | |
| axilReadSlaves | AxiLiteReadSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) | |
| sAxisMaster | AxiStreamMasterType | |
| sAxisSlave | AxiStreamSlaveType | |
| mAxisMaster | AxiStreamMasterType | |
| mAxisSlave | AxiStreamSlaveType |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| GET_BUILD_INFO_C | BuildInfoRetType | toBuildInfo(BUILD_INFO_C) | |
| MOD_BUILD_INFO_C | BuildInfoRetType | ( buildString => GET_BUILD_INFO_C.buildString, fwVersion => x"1234_5678", -- force FW version gitHash => x"1111_2222_3333_4444_5555_6666_7777_8888_9999_AAAA") |
|
| SIM_BUILD_INFO_C | slv(2239 downto 0) | toSlv(MOD_BUILD_INFO_C) | Force githash |
| CLK_PERIOD_C | time | 10 ns | |
| TPD_G | time | CLK_PERIOD_C/4 | |
| MAX_TID_C | natural | 3 | |
| AXIS_CONFIG_C | AxiStreamConfigType | ssiAxiStreamConfig(32) | |
| NUM_AXIL_MASTERS_C | natural | 1 | |
| VERSION_INDEX_C | natural | 0 | |
| AXIL_CONFIG_C | AxiLiteCrossbarMasterConfigArray(NUM_AXIL_MASTERS_C-1 downto 0) | genAxiLiteConfig(NUM_AXIL_MASTERS_C, x"0000_0000", 16, 12) |
|
| REG_INIT_C | RegType | ( tid => (others => '0'), sAxisMaster => AXI_STREAM_MASTER_INIT_C, mAxisSlave => AXI_STREAM_SLAVE_INIT_C, state => REQ_S) |
Types
| Name | Type | Description |
|---|---|---|
| StateType | ( REQ_S, RESP_S) |
|
| RegType |
Processes
- comb: ( mAxisMaster, r, rst, sAxisSlave )
- seq: ( clk )
Instantiations
- U_ClkRst: surf.ClkRst
- U_SRPv3: surf.SrpV3AxiLite
Description
Module Being Tested
- U_XBAR: surf.AxiLiteCrossbar
Description
AXI-Lite Crossbar Module
- U_AxiVersion: surf.AxiVersion