Entity: SrpV3AxiTb

Diagram

Description

Company : SLAC National Accelerator Laboratory

Description: Simulation testbed for SrpV3Axi

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Signals

Name Type Description
r RegType
rin RegType
clk sl
rst sl
axiWriteMaster AxiWriteMasterType
axiWriteSlave AxiWriteSlaveType
axiReadMaster AxiReadMasterType
axiReadSlave AxiReadSlaveType
srpIbMaster AxiStreamMasterType
srpIbSlave AxiStreamSlaveType
srpObMaster AxiStreamMasterType
srpObSlave AxiStreamSlaveType
txMaster AxiStreamMasterType
txSlave AxiStreamSlaveType
rxMaster AxiStreamMasterType
rxSlave AxiStreamSlaveType
passed sl
failed sl

Constants

Name Type Value Description
FSM_AXIS_CONFIG_C AxiStreamConfigType ssiAxiStreamConfig(4) 32-bit data width
SRP_AXIS_CONFIG_C AxiStreamConfigType ssiAxiStreamConfig(8) 64-bit data width
AXI_CONFIG_C AxiConfigType ( ADDR_WIDTH_C => 12,
-- 4kB RAM DATA_BYTES_C => 8,
-- 64-bit data width ID_BITS_C => 1,
LEN_BITS_C => 8)
REQ_BYTE_SIZE_C positive (2**AXI_CONFIG_C.ADDR_WIDTH_C)
REQ_WORD_SIZE_C positive (REQ_BYTE_SIZE_C/4)
CLK_PERIOD_C time 10 ns
TPD_G time (CLK_PERIOD_C/4)
REG_INIT_C RegType ( opCode => x"02",
-- posted write = 0x2 cnt => 0,
tid => x"1234_0000",
addr => (others => '0'),
txMaster => AXI_STREAM_MASTER_INIT_C,
rxSlave => AXI_STREAM_SLAVE_INIT_C,
state => REQ_MSG,
passed => '0',
failed => '0')

Types

Name Type Description
StateType ( REQ_MSG,
TX_PAYLOAD,
RX_HDR,
RX_PAYLOAD,
FAILED_S,
PASSED_S)
RegType

Processes

Instantiations