Entity: SspDecoder8b10bTb
- File: SspDecoder8b10bTb.vhd
Diagram
Description
Company : SLAC National Accelerator Laboratory
Description: Testbench for design "SspDecoder8b10b"
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Signals
| Name | Type | Description |
|---|---|---|
| clkDiv2 | sl | component ports |
| clk | sl | |
| rst | sl | |
| dataIn | slv(19 downto 0) | |
| validIn | sl | |
| dataOut | slv(15 downto 0) | |
| validOut | sl | |
| sof | sl | |
| eof | sl | |
| eofe | sl | |
| dataInEnc | slv(15 downto 0) | |
| dataValidEnc | sl | |
| dataOutEnc | slv(19 downto 0) |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| TPD_G | time | 1 ns | |
| RST_POLARITY_G | sl | '1' | |
| RST_ASYNC_G | boolean | true |
Processes
- WaveGen_Proc: ( )
Description
waveform generation
Instantiations
- Stimuli: surf.SspEncoder8b10b
- Fifo: surf.FifoCascade
Description
async fifo for validIn simulation
- UUT: surf.SspDecoder8b10b
Description
unit under test