Entity: SynchronizerFifoTb

Diagram

Description

Company : SLAC National Accelerator Laboratory

Description: Simulation Testbed for the SynchronizerFifo module

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Signals

Name Type Description
wr_clk sl Internal signals
rd_clk sl
wr_en sl Test signals
rd_en sl
din slv(DATA_WIDTH_C-1 downto 0)
dout slv(DATA_WIDTH_C-1 downto 0)
wr_data_count slv(ADDR_WIDTH_C-1 downto 0)
rd_data_count slv(ADDR_WIDTH_C-1 downto 0)
valid sl
error sl
readDone sl
writeDone sl
readCnt slv(DATA_WIDTH_C-1 downto 0)
writeCnt slv(DATA_WIDTH_C-1 downto 0)
rst sl
initRst sl
reset sl

Constants

Name Type Value Description
WRITE_CLK_ARRAY_C TestClkType ( 5 ns,
20 ns,
10 ns,
10 ns,
3.1415926535897932384626433832795 ns)
READ_CLK_ARRAY_C TestClkType ( 20 ns,
5 ns,
10 ns,
3.1415926535897932384626433832795 ns,
10 ns)
CLK_SEL_C integer 2 change this parameter for simulating different clock configurations
WRITE_CLK_C time WRITE_CLK_ARRAY_C(CLK_SEL_C)
READ_CLK_C time READ_CLK_ARRAY_C(CLK_SEL_C)
MEMORY_TYPE_G string "block"
FWFT_EN_C boolean true
DATA_WIDTH_C integer 8
ADDR_WIDTH_C integer 2
TPD_C time 1 ns
MAX_VALUE_C slv(DATA_WIDTH_C-1 downto 0) conv_std_logic_vector((2**8)-1,
DATA_WIDTH_C)

Types

Name Type Description
TestClkType

Processes

Description
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Instantiations

Description
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