Description: Wrapper for multiple SynchronizerOneShotCnt modules
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Generics
Generic name
Type
Value
Description
TPD_G
time
1 ns
Simulation FF output delay
RST_POLARITY_G
sl
'1'
'1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G
boolean
false
true if reset is asynchronous, false if reset is synchronous
COMMON_CLK_G
boolean
false
True if wrClk and rdClk are the same clock
IN_POLARITY_G
slv
"1"
0 for active LOW, 1 for active HIGH (dataIn port)
OUT_POLARITY_G
slv
"1"
0 for active LOW, 1 for active HIGH (dataOut port)
USE_DSP_G
string
"no"
"no" for no DSP implementation, "yes" to use DSP slices
SYNTH_CNT_G
slv
"1"
Set to 1 for synthesising counter RTL, '0' to not synthesis the counter
CNT_RST_EDGE_G
boolean
true
true if counter reset should be edge detected, else level detected