Entity: TenGigEthGtx7Wrapper

Diagram

time TPD_G natural range 1 to 4 NUM_LANE_G boolean PAUSE_EN_G boolean USE_GTREFCLK_G boolean REFCLK_DIV2_G bit_vector QPLL_REFCLK_SEL_G boolean EN_AXI_REG_G AxiStreamConfigArray(3 downto 0) AXIS_CONFIG_G Slv48Array(NUM_LANE_G-1 downto 0) localMac slv(NUM_LANE_G-1 downto 0) dmaClk slv(NUM_LANE_G-1 downto 0) dmaRst AxiStreamSlaveArray(NUM_LANE_G-1 downto 0) dmaIbSlaves AxiStreamMasterArray(NUM_LANE_G-1 downto 0) dmaObMasters slv(NUM_LANE_G-1 downto 0) axiLiteClk slv(NUM_LANE_G-1 downto 0) axiLiteRst AxiLiteReadMasterArray(NUM_LANE_G-1 downto 0) axiLiteReadMasters AxiLiteWriteMasterArray(NUM_LANE_G-1 downto 0) axiLiteWriteMasters slv(NUM_LANE_G-1 downto 0) sigDet slv(NUM_LANE_G-1 downto 0) txFault sl extRst slv(4 downto 0) gtTxPreCursor slv(4 downto 0) gtTxPostCursor slv(3 downto 0) gtTxDiffCtrl sl gtRxPolarity sl gtTxPolarity sl gtRefClk sl gtClkP sl gtClkN slv(NUM_LANE_G-1 downto 0) gtRxP slv(NUM_LANE_G-1 downto 0) gtRxN AxiStreamMasterArray(NUM_LANE_G-1 downto 0) dmaIbMasters AxiStreamSlaveArray(NUM_LANE_G-1 downto 0) dmaObSlaves AxiLiteReadSlaveArray(NUM_LANE_G-1 downto 0) axiLiteReadSlaves AxiLiteWriteSlaveArray(NUM_LANE_G-1 downto 0) axiLiteWriteSlaves slv(NUM_LANE_G-1 downto 0) txDisable sl phyClk sl phyRst slv(NUM_LANE_G-1 downto 0) phyReady sl gtClk slv(NUM_LANE_G-1 downto 0) gtTxP slv(NUM_LANE_G-1 downto 0) gtTxN

Description

Company : SLAC National Accelerator Laboratory

Description: Gtx7 Wrapper for 10GBASE-R Ethernet

Note: This module supports up to a MGT QUAD of 10GigE interfaces

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Generics

Generic name Type Value Description
TPD_G time 1 ns
NUM_LANE_G natural range 1 to 4 1
PAUSE_EN_G boolean true
USE_GTREFCLK_G boolean false FALSE: gtClkP/N, TRUE: gtRefClk
REFCLK_DIV2_G boolean false FALSE: gtClkP/N = 156.25 MHz, TRUE: gtClkP/N = 312.5 MHz
QPLL_REFCLK_SEL_G bit_vector "001"
EN_AXI_REG_G boolean false AXI-Lite Configurations
AXIS_CONFIG_G AxiStreamConfigArray(3 downto 0) (others => EMAC_AXIS_CONFIG_C) AXI Streaming Configurations

Ports

Port name Direction Type Description
localMac in Slv48Array(NUM_LANE_G-1 downto 0) Local Configurations
dmaClk in slv(NUM_LANE_G-1 downto 0) Streaming DMA Interface
dmaRst in slv(NUM_LANE_G-1 downto 0)
dmaIbMasters out AxiStreamMasterArray(NUM_LANE_G-1 downto 0)
dmaIbSlaves in AxiStreamSlaveArray(NUM_LANE_G-1 downto 0)
dmaObMasters in AxiStreamMasterArray(NUM_LANE_G-1 downto 0)
dmaObSlaves out AxiStreamSlaveArray(NUM_LANE_G-1 downto 0)
axiLiteClk in slv(NUM_LANE_G-1 downto 0) Slave AXI-Lite Interface
axiLiteRst in slv(NUM_LANE_G-1 downto 0)
axiLiteReadMasters in AxiLiteReadMasterArray(NUM_LANE_G-1 downto 0)
axiLiteReadSlaves out AxiLiteReadSlaveArray(NUM_LANE_G-1 downto 0)
axiLiteWriteMasters in AxiLiteWriteMasterArray(NUM_LANE_G-1 downto 0)
axiLiteWriteSlaves out AxiLiteWriteSlaveArray(NUM_LANE_G-1 downto 0)
sigDet in slv(NUM_LANE_G-1 downto 0) SFP+ Ports
txFault in slv(NUM_LANE_G-1 downto 0)
txDisable out slv(NUM_LANE_G-1 downto 0)
extRst in sl Misc. Signals
phyClk out sl
phyRst out sl
phyReady out slv(NUM_LANE_G-1 downto 0)
gtTxPreCursor in slv(4 downto 0) Transceiver Debug Interface
gtTxPostCursor in slv(4 downto 0)
gtTxDiffCtrl in slv(3 downto 0)
gtRxPolarity in sl
gtTxPolarity in sl
gtRefClk in sl 156.25 MHz only
gtClkP in sl
gtClkN in sl
gtClk out sl
gtTxP out slv(NUM_LANE_G-1 downto 0) MGT Ports
gtTxN out slv(NUM_LANE_G-1 downto 0)
gtRxP in slv(NUM_LANE_G-1 downto 0)
gtRxN in slv(NUM_LANE_G-1 downto 0)

Signals

Name Type Description
phyClock sl
phyReset sl
qplllock sl
qplloutclk sl
qplloutrefclk sl
qpllRst slv(NUM_LANE_G-1 downto 0)
qpllReset sl

Instantiations

Description

Common Clock Module