Entity: TrueDualPortRamAlteraMf

Diagram

time TPD_G boolean COMMON_CLK_G sl RST_POLARITY_G string MEMORY_TYPE_G natural range 0 to 100 READ_LATENCY_G integer range 1 to (2**24) DATA_WIDTH_G boolean BYTE_WR_EN_G integer range 8 to 9 BYTE_WIDTH_G integer range 1 to (2**24) ADDR_WIDTH_G sl clka sl ena slv(ite(BYTE_WR_EN_G, wordCount(DATA_WIDTH_G, BYTE_WIDTH_G), 1)-1 downto 0) wea sl regcea sl rsta slv(ADDR_WIDTH_G-1 downto 0) addra slv(DATA_WIDTH_G-1 downto 0) dina sl clkb sl enb slv(ite(BYTE_WR_EN_G, wordCount(DATA_WIDTH_G, BYTE_WIDTH_G), 1)-1 downto 0) web sl regceb sl rstb slv(ADDR_WIDTH_G-1 downto 0) addrb slv(DATA_WIDTH_G-1 downto 0) dinb slv(DATA_WIDTH_G-1 downto 0) douta slv(DATA_WIDTH_G-1 downto 0) doutb

Description


Company : SLAC National Accelerator Laboratory

Description: Wrapper for XPM Simple Dual Port RAM

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Generics

Generic name Type Value Description
TPD_G time 1 ns
COMMON_CLK_G boolean false
RST_POLARITY_G sl '1' '1' for active high rst, '0' for active low
MEMORY_TYPE_G string "block"
READ_LATENCY_G natural range 0 to 100 1
DATA_WIDTH_G integer range 1 to (2**24) 16
BYTE_WR_EN_G boolean false
BYTE_WIDTH_G integer range 8 to 9 8 If BRAM, should be multiple or 8 or 9
ADDR_WIDTH_G integer range 1 to (2**24) 4

Ports

Port name Direction Type Description
clka in sl Port A
ena in sl
wea in slv(ite(BYTE_WR_EN_G, wordCount(DATA_WIDTH_G, BYTE_WIDTH_G), 1)-1 downto 0)
regcea in sl
rsta in sl
addra in slv(ADDR_WIDTH_G-1 downto 0)
dina in slv(DATA_WIDTH_G-1 downto 0)
douta out slv(DATA_WIDTH_G-1 downto 0)
clkb in sl Port B
enb in sl
web in slv(ite(BYTE_WR_EN_G, wordCount(DATA_WIDTH_G, BYTE_WIDTH_G), 1)-1 downto 0)
regceb in sl
rstb in sl
addrb in slv(ADDR_WIDTH_G-1 downto 0)
dinb in slv(DATA_WIDTH_G-1 downto 0)
doutb out slv(DATA_WIDTH_G-1 downto 0)