Entity: UartAxiLiteMasterFsm

Diagram

time TPD_G sl axilClk sl axilRst sl uartTxReady sl uartRxValid slv(7 downto 0) uartRxData AxiLiteWriteSlaveType mAxilWriteSlave AxiLiteReadSlaveType mAxilReadSlave sl uartTxValid slv(7 downto 0) uartTxData sl uartRxReady AxiLiteWriteMasterType mAxilWriteMaster AxiLiteReadMasterType mAxilReadMaster

Description


Title : UART Memory Protocol: https://confluence.slac.stanford.edu/x/uSDoDQ

Company : SLAC National Accelerator Laboratory

Description: Finite State Machine (FSM) for UartAxiLiteMaster.vhd

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Generics

Generic name Type Value Description
TPD_G time 1 ns

Ports

Port name Direction Type Description
axilClk in sl Clock and Reset
axilRst in sl
uartTxValid out sl UART TX Streaming Byte Interface
uartTxData out slv(7 downto 0)
uartTxReady in sl
uartRxValid in sl UART RX Streaming Byte Interface
uartRxData in slv(7 downto 0)
uartRxReady out sl
mAxilWriteMaster out AxiLiteWriteMasterType AXI-Lite interface
mAxilWriteSlave in AxiLiteWriteSlaveType
mAxilReadMaster out AxiLiteReadMasterType
mAxilReadSlave in AxiLiteReadSlaveType

Signals

Name Type Description
r RegType
rin RegType
axilAck AxiLiteAckType

Constants

Name Type Value Description
REG_INIT_C RegType ( state => WAIT_START_S,
count => (others => '0'),
axilReq => AXI_LITE_REQ_INIT_C,
rdData => (others => '0'),
uartTxData => (others => '0'),
uartTxValid => '0',
uartRxReady => '1')

Types

Name Type Description
StateType ( WAIT_START_S,
SPACE_ADDR_S,
ADDR_SPACE_S,
WR_DATA_S,
WAIT_EOL_S,
AXIL_TXN_S,
RD_DATA_SPACE_S,
RD_DATA_S,
DONE_S)
RegType

Functions

Description
translate a hex character 0-9 A-F into an slv

Processes

Description
[in]

Instantiations