Entity: UartAxiLiteMasterTb
- File: UartAxiLiteMasterTb.vhd
Diagram
Description
Company : SLAC National Accelerator Laboratory
Description: Testbench for design "UartAxiLiteMaster"
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Signals
| Name | Type | Description |
|---|---|---|
| axilWriteMaster | AxiLiteWriteMasterType | [out] |
| axilWriteSlave | AxiLiteWriteSlaveType | [in] |
| axilReadMaster | AxiLiteReadMasterType | [out] |
| axilReadSlave | AxiLiteReadSlaveType | [in] |
| tx | sl | [out] |
| rx | sl | [in] |
| clk | sl | [in] |
| rst | sl | [in] |
| wrData | slv(7 downto 0) | [in] |
| wrValid | sl | [in] |
| wrReady | sl | [out] |
| rdData | slv(7 downto 0) | [out] |
| rdValid | sl | [out] |
| rdReady | sl |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| TPD_G | time | 1 ns | |
| CLK_FREQ_G | real | 125.0e6 | |
| BAUD_RATE_G | integer | 115200 | |
| MEMORY_TYPE_G | string | "distributed" | |
| FIFO_ADDR_WIDTH_G | integer range 4 to 48 | 5 |
Processes
- test: ( )
Description
[out]
Instantiations
- U_ClkRst_1: surf.ClkRst
- U_UartWrapper_1: surf.UartWrapper
- U_UartAxiLiteMaster: surf.UartAxiLiteMaster
Description
[in]
component instantiation
- U_AxiDualPortRam_1: surf.AxiDualPortRam
Description
[in]