Entity: UdpDebugBridge

Diagram

STD_LOGIC axisClk STD_LOGIC axisRst STD_LOGIC \mAxisReq[tValid]\ STD_LOGIC_VECTOR ( 511 downto 0 ) \mAxisReq[tData]\ STD_LOGIC_VECTOR ( 63 downto 0 ) \mAxisReq[tStrb]\ STD_LOGIC_VECTOR ( 63 downto 0 ) \mAxisReq[tKeep]\ STD_LOGIC \mAxisReq[tLast]\ STD_LOGIC_VECTOR ( 7 downto 0 ) \mAxisReq[tDest]\ STD_LOGIC_VECTOR ( 7 downto 0 ) \mAxisReq[tId]\ STD_LOGIC_VECTOR ( 511 downto 0 ) \mAxisReq[tUser]\ STD_LOGIC \sAxisTdo[tReady]\ STD_LOGIC \sAxisReq[tReady]\ STD_LOGIC \mAxisTdo[tValid]\ STD_LOGIC_VECTOR ( 511 downto 0 ) \mAxisTdo[tData]\ STD_LOGIC_VECTOR ( 63 downto 0 ) \mAxisTdo[tStrb]\ STD_LOGIC_VECTOR ( 63 downto 0 ) \mAxisTdo[tKeep]\ STD_LOGIC \mAxisTdo[tLast]\ STD_LOGIC_VECTOR ( 7 downto 0 ) \mAxisTdo[tDest]\ STD_LOGIC_VECTOR ( 7 downto 0 ) \mAxisTdo[tId]\ STD_LOGIC_VECTOR ( 511 downto 0 ) \mAxisTdo[tUser]\

Description

Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018 Date : Wed Jun 26 13:06:07 2019 Host : rdsrv107.slac.stanford.edu running 64-bit Red Hat Enterprise Linux Server release 6.10 (Santiago) Command : write_vhdl -force -mode synth_stub /u/re/ruckman/projects/dpm-remote-ibert-tester/firmware/submodules/xvc-udp-debug-bridge/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd Design : UdpDebugBridge Purpose : Stub declaration of top-level module interface

Device : xcku040-ffva1156-2-e

Ports

Port name Direction Type Description
axisClk in STD_LOGIC
axisRst in STD_LOGIC
\mAxisReq[tValid]</td> in STD_LOGIC
\mAxisReq[tData]</td> in STD_LOGIC_VECTOR ( 511 downto 0 )
\mAxisReq[tStrb]</td> in STD_LOGIC_VECTOR ( 63 downto 0 )
\mAxisReq[tKeep]</td> in STD_LOGIC_VECTOR ( 63 downto 0 )
\mAxisReq[tLast]</td> in STD_LOGIC
\mAxisReq[tDest]</td> in STD_LOGIC_VECTOR ( 7 downto 0 )
\mAxisReq[tId]</td> in STD_LOGIC_VECTOR ( 7 downto 0 )
\mAxisReq[tUser]</td> in STD_LOGIC_VECTOR ( 511 downto 0 )
\sAxisReq[tReady]</td> out STD_LOGIC
\mAxisTdo[tValid]</td> out STD_LOGIC
\mAxisTdo[tData]</td> out STD_LOGIC_VECTOR ( 511 downto 0 )
\mAxisTdo[tStrb]</td> out STD_LOGIC_VECTOR ( 63 downto 0 )
\mAxisTdo[tKeep]</td> out STD_LOGIC_VECTOR ( 63 downto 0 )
\mAxisTdo[tLast]</td> out STD_LOGIC
\mAxisTdo[tDest]</td> out STD_LOGIC_VECTOR ( 7 downto 0 )
\mAxisTdo[tId]</td> out STD_LOGIC_VECTOR ( 7 downto 0 )
\mAxisTdo[tUser]</td> out STD_LOGIC_VECTOR ( 511 downto 0 )
\sAxisTdo[tReady]</td> in STD_LOGIC